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LPC47M14X 数据表(PDF) 29 Page - SMSC Corporation |
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LPC47M14X 数据表(HTML) 29 Page - SMSC Corporation |
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29 / 205 page ![]() SMSC DS – LPC47M14X Page 29 Rev. 03/19/2001 BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". PS/2 Model 30 Mode BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 6 5 4 3 2 1 0 MOT EN3 MOT EN2 MOT EN1 MOT EN0 DMAEN nRESET DRIVE SEL1 DRIVE SEL0 RESET COND. 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 nDRV2 nDS1 nDS0 WDATA F/F RDATA F/F WGATE F/F nDS3 nDS2 RESET COND. N/A 1 1 0 0 0 1 1 |
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