LPC47M14X datasheet(34/205 Pages) SMSC

34 / 205 page

SMSC DS – LPC47M14X

Page 34

Rev. 03/19/2001

MAIN STATUS REGISTER

Address 3F4 READ ONLY

The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register

can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It

should be read before each byte transferring to or from the data register except in DMA mode. No delay is required

when reading the MSR after a data transfer.

RQM

DIO

NON

DMA

CMD

BUSY

Reserved Reserved

DRV1

BUSY

DRV0

BUSY

BIT 0 - 1 DRV x BUSY

These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and

recalibrates.

BIT 4 COMMAND BUSY

This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted

and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is

returned to a 0 after the last command byte.

BIT 5 NON-DMA

Reserved, read ‘0’. This part does not support non-DMA mode.

BIT 6 DIO

Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.

BIT 7 RQM

Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.

DATA REGISTER (FIFO)

Address 3F5 READ/WRITE

All command parameter information, disk data and result status are transferred between the host processor and the

floppy disk controller through the Data Register.

Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled mode after any form of reset.

This maintains PC/AT hardware

compatibility. The default values can be changed through the Configure command (enable full FIFO operation with

threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk

error. Table 12 gives several examples of the delays with a FIFO.

The data is based upon the following formula:

Threshold # x

DATA

RATE

x 8

- 1.5

µs =

DELAY

At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the

RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that

invalid data is not transferred.

LPC47M14X 数据表(PDF) 34 Page - SMSC Corporation

LPC47M14X 数据表(HTML) 34 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

LPC47M14X 数据表(PDF) 34 Page - SMSC Corporation

LPC47M14X 数据表(HTML) 34 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载