LPC47M14X datasheet(77/205 Pages) SMSC

77 / 205 page

SMSC DS – LPC47M14X

Page 77

Rev. 03/19/2001

command acknowledge will appear first, before any unread FIFO data. In the examples above, the receive FIFO is

cleared before the command acknowledge byte is placed in the MIDI Data port read buffer.

6.8.6

MIDI UART

Overview

The UART is used to transmit and receive MIDI protocol data from the MIDI Data port in the Host Interface (see

Section “Host Interface”).

The MIDI protocol requires 31.25k Baud (

±1%) and 10 bits total per frame: 1 start bit, 8 data bits, no parity, and 1

stop bit. For example, there are 320 microseconds per serial MIDI data byte. MIDI data is transferred LSB first

(Figure 7).

The UART is configured in full-duplex mode for the MPU-401 MIDI Interface, with 16-byte send/receive FIFOs.

MIDI RX CLOCK

MIDI RX DATA BYTE (01H)

MIDI_IN

FIGURE 5 - MIDI DATA BYTE EXAMPLE

Note

1: MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32µs.

6.8.7

MPU-401 Configuration Registers

The LPC47M14x configuration registers are in Logical Device B (see “Configuration” section). The configuration

registers contain the MPU-401 Activate, Base Address and Interrupt select. The defaults for the Base Address and

Interrupt Select configuration registers match the MPU-401 factory defaults.

Activate and I/O Base Address

When the Activate bit D0 is ‘0’, the MPU-401 I/O base address decoder is disabled, the IRQ is always deasserted,

and the MPU-401 hardware is in a minimum power-consumption state. When the Activate bit is ‘1’, the MPU-401 I/O

base address decoder and the IRQ are enabled, and the MPU-401 hardware is fully powered.

Byte. The MPU-401 I/O base address is programmable on even-byte boundaries. The valid MPU-401 I/O base

address range is 0x0100 – 0x0FFE. See Section “Host Interface”.

LPC47M14X 数据表(PDF) 77 Page - SMSC Corporation