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STPMIC1 数据表(PDF) 121 Page - STMicroelectronics

部件名 STPMIC1
功能描述  Highly integrated power management IC for micro processor units
PDF  140 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPMIC1 数据表(HTML) 121 Page - STMicroelectronics

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6.7.4
NVM LDOs rank shadow register 2 (NVM_LDOS_RANK_SHR2)
Table 68. NVM_LDOS_RANK_SHR2
7
6
5
4
3
2
1
0
BUCK4_CLAMP
LDO3_BYPASS
REFDDR_RANK[1:0]
LDO6_RANK[1:0]
LDO5_RANK[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address: 0xFB
Type: read write register
Default: depends on part number refer to Table 64. NVM shadow register map
Description: NVM LDOs rank shadow register 2
[7]
BUCK4_CLAMP: Clamp Buck4 output value to 1.3 V max.
0: VOUT[5:0] of Buck4 is not clamped
1: VOUT[5:0] of Buck4 is clamped to b011100 (1.3 V)
[6]
LDO3_BYPASS: LDO3 forced bypass mode
0: LDO3 not in bypass mode
1: LDO3 in bypass mode
[5:4]
REFDDR_RANK[1:0]:
00: rank0
01: rank1
10: rank2
11: rank3
[3:2]
LDO6_RANK[1:0]:
00: rank0
01: rank1
10: rank2
11: rank3
[1:0]
LDO5_RANK[1:0]:
00: rank0
01: rank1
10: rank2
11: rank3
STPMIC1
NVM shadow registers
DS12792 - Rev 7
page 121/140



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