Data Sheet

ADE1201

Rev. 0 | Page 11 of 40

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. NC = NO CONNECT. THESE PINS ARE INTERNALLY CONNECTED AND

IT IS RECOMMENDED TO TIE THESE PINS TO GNDF EXTERNALLY.

2. NIC = NOT INTERNALLY CONNECTED.

1 2 3456 7 89 10

11

12

13

14

15

16

17

18

19

20

ADE1201

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 13. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GNDF

The GNDF pin located at Pin 1 is used to provide a return path for current from the internal programmable

load. Both Pin 1 and Pin 10 must be connected to ground externally. See the Layout Guidelines section for

recommendations on how to connect this pin. Do not tie the GNDF pins from multiple ADE1201 application

circuits together if ac or negative dc inputs are applied.

2

GATE

Use this pin to drive the gate pin of an enhancement mode field effect transistor (FET).

3

LOAD1

Programmable Load. Use this pin to command a preset current required for loading the relay contacts.

4

NIC

Not Internally Connected.

5

IN1

Digital Input Pin. The scaled input signal is applied at this pin.

6, 8

NC

No Connect. These pins are internally connected and it is recommended to tie these pins to GNDF externally.

7

VDDL

1.8 V Output of the Analog Low Dropout (LDO) Regulator. Do not connect external load circuitry to this pin.

Decouple this pin to GNDF with the recommended capacitors shown in Table 16, and see the Layout

Guidelines section for recommendations on how to connect this pin.

9

VDDI

Isolated Secondary Side Power Supply Output Pin. This pin provides access to the 2.0 V, on-chip isolated power

supply. Decouple this pin to GNDF with the recommended capacitors shown in Table 16, and see the Layout

Guidelines section for recommendations on how to connect this pin. Do not connect external load circuitry to

this pin.

10

GNDF

The GNDF pin located at Pin 10 is used as a reference for the internal, isolated power supply and the LDO regulator.

Both Pin 1 and Pin 10 must be connected to ground externally. See the Layout Guidelines section for

recommendations on how to connect this pin. Do not tie the GNDF pins from multiple ADE1201 application

circuits together if ac or negative dc inputs are applied.

11

GND

GND Pin. This pin is the system controller side ground pin.

12

VDD

Primary Supply Voltage. This pin provides the supply voltage for the ADE1201. Maintain the supply voltage at

3.3 V ± 10% for specified operation. Decouple this pin to the GND pin with the recommended capacitors

shown in Table 16, and see the Layout Guidelines section for recommendations on how to connect this pin.

13

VLDO

1.8 V Output of the LDO Regulator. Decouple this pin to the GND pin with the recommended capacitors shown

in Table 16, and see the Layout Guidelines section for recommendations on how to connect this pin. Do not

connect external load circuitry to this pin.

14

DOUT1

15

IRQ

Interrupt Pin. This pin is open-drain and a 10 kΩ pull-up resistor to the VDD supply voltage is recommended.

16

ADDR

Address Mode Pin. This pin is used for multichip addressing. If multichip addressing is not used, connect this pin

to ground. The address divider requires 1% resistors, as described in the SPI ADE1201 Addressing section.

17

CS

Chip Select for SPI Port.

18

SCLK

Serial Clock Input for SPI Port. All serial data transfers are synchronized to this clock.

19

MOSI

Data Input for SPI Port.

20

MISO

Data Output for SPI Port.