ADE1201 datasheet(18/40 Pages) AD

18 / 40 page

ADE1201

Data Sheet

Rev. 0 | Page 18 of 40

Table 15. Decimation Settings

DECRATE Bit Setting

Number of Samples

Bypass the decimator

AVERAGED BY N

DECIMATED BY N

Figure 24. Decimation Filter Topology

Digital Datapaths

Four datapaths process the data coming out of the decimator,

including comparators and debounce filtering.

One datapath, DOUT1, is capable of driving the DOUT1

output, as shown in Figure 23. The output can also be read over

the SPI.

Three additional datapaths, WARNA1, WARNB1, and

WARNC1 are provided for the user to configure warnings. The

output of the warning datapaths can be read over the SPI.

Set Bit 15 of the BIN_FILTER, WARNA_FILTER,

WARNB_FILTER, and WARNC_FILTER registers to enable

the comparator and debounce filters.

Comparator Function

Each comparator includes a high threshold level and a low

threshold level. The thresholds are programmable between 0x00

and 0xFF. An IN1 pin voltage of 1.25 V/PGA setting translates

to 0xFF. To calculate the threshold register value based on the

desired threshold voltage and input signal level, use the

following equation:

THR = (THRESHOLD/(1.25/PGA)) × 255

(1)

where:

THR is the value that is written in the BIN_THR, WARNA_THR,

WARNB_THR, and WARNC_THR control registers.

THRESHOLD is the desired threshold level expressed in V.

PGA is the PGA gain selected by the PGA_GAIN register.

The BIN_THR register contains the configuration used for the

DOUT1 datapath, which can be output on the DOUT1 pin.

The WARNA_THR, WARNB_THR, and WARNC_THR

registers contain the configuration for the warning channels.

Each comparator has four configurable modes: hysteretic mode,

midrange mode, greater than (GT) mode, and lesser than

(LT) mode. They are selected by the BIN_MODE, WARNA_

MODE, WARNB_MODE, and WARNC_MODE bits in the

BIN_CTRL register. After reset, the DOUT1 channel is in

hysteretic mode, the WARNA1 channel is in GT mode, the

WARNB1 channel is in midrange mode, and the WARNC1

channel is in LT mode.

Comparator in Hysteretic Output Mode

In hysteretic output mode, when the ADC output is greater

than the high threshold level of the comparator, the output is set

high. The output is set low when the ADC output drops below

the low threshold level. The behavior of the comparator in the

hysteretic output mode is shown in Figure 25.

TIME

HIGH THRESHOLD

LEVEL

LOW THRESHOLD

LEVEL

ADC

OUTPUT

COMPARATOR

OUTPUT

TIME

Figure 25. Comparator Behavior in Hysteretic Output Mode

Comparator in Midrange Output Mode

In midrange output mode, when the ADC output is less than

the high threshold level and greater than the low threshold level,

the comparator output is set high. The output is set low when

the ADC output drops below the low threshold level or goes

above the high threshold level. The behavior of the comparator

in the midrange output mode is shown in Figure 26.

TIME

HIGH THRESHOLD

LEVEL

LOW THRESHOLD

LEVEL

ADC

OUTPUT

COMPARATOR

OUTPUT

TIME

Figure 26. Comparator Behavior in Midrange Output Mode

ADE1201 数据表(PDF) 18 Page - Analog Devices

ADE1201 数据表(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载

链接网址

ADE1201 数据表(PDF) 18 Page - Analog Devices

ADE1201 数据表(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表 下载

链接网址

数据表下载