ADE1201 datasheet(24/40 Pages) AD

24 / 40 page

ADE1201

Data Sheet

Rev. 0 | Page 24 of 40

THERMAL SHUTDOWN

If the junction temperature of the isolated side exceeds the

thermal shutdown value given in Table 1, the programmable load

current is disabled. The TSD bit in the INT_STATUS register

indicates if the device is in thermal shutdown condition. When the

device cools down by the hysteresis value given in Table 1, the

programmable load current is reenabled.

INTERRUPT

The IRQ output is open-drain, not push-pull.

The IRQ pin is managed by a 16-bit interrupt mask register,

MASK. To enable an interrupt, the corresponding bit in the

MASK register must be set to 1. To disable an interrupt, the bit

must be cleared to 0.

INT_STATUS Register

When an interrupt is triggered, the IRQ pin goes low. To

determine the source of the interrupt, read the INT_STATUS

in the INT_STATUS register, write to the INT_STATUS register

with the corresponding bits set to 1. The IRQ pin remains low

until the corresponding INT_STATUS flag is cleared.

By default, all interrupts are disabled except for the RSTDONE

interrupt. This interrupt cannot be disabled (masked).

During power-up or software reset, the IRQ pin stays high.

When the power-up or software reset ends, the IRQ pin goes low

and Bit 14 (RSTDONE) in the INT_STATUS register is set to 1.

Note that Bit 15 (DREADY) in the MASK register functions

differently than Bits[14:0]. See the SAR ADC section more

information on the DREADY function.

STATUS Register

The STATUS register contains status flags that are updated in

real time. When the condition related to a flag is triggered, the

flag is set to 1. When the condition disappears, the flag is

automatically cleared to 0.

The bits in the STATUS register are identical to the bits in the

INT_STATUS register with one exception. Bit 14 is RSTBUSY

in the STATUS register and RSTDONE in the INT_STATUS

becomes 0 when the IC is ready to accept commands.

SPI PROTOCOL OVERVIEW

The compatible SPI consists of four pins: SCLK, MOSI, MISO, and

CS. The ADE1201 is always an SPI slave. The SPI is compatible

with 16-bit read/write operations. The maximum serial clock

frequency supported by this interface is 10 MHz.

The CS input pin is the chip select input. Drive the CS pin low

for the entire data transfer operation. Bring the CS pin high

during a data transfer operation to abort the transfer and place

the serial bus in a high impedance state. A new transfer can be

initiated by returning the CS pin to low.

Data shifts into the device at the MOSI pin on the falling edge

of SCLK, and the ADE1201 samples the data on the rising edge

of SCLK. Data shifts out of the ADE1201 at the MISO pin on

the falling edge of SCLK, and the host controller samples the

data on the rising edge of SCLK. The MSB of the word is shifted

in and out first. MISO stays in high impedance when no data is

transmitted from the ADE1201.

Figure 35 shows the connection between the ADE1201 SPI and

a host controller with a master SPI.

ADE1201

MOSI

SCLK

SPI DEVICE

MOSI

SCLK

MISO

Figure 35. Connecting the SPI to an SPI Device

SPI ADE1201 Addressing

Up to eight ADE1201 devices can be accessed on the same SPI

bus. A voltage ladder of up to seven equal resistors ranging

from 1 kΩ to 10 kΩ values with 1% tolerance can be used (see

Figure 37). With the ADDR pin connected to 3.3 V, the ADE1201

has the chip address of 7. With the ADDR pin connected to

ground, the ADE1201 has the chip address of 0. The remaining

six ADE1201 devices have the chip addresses in sequence based

on the applied voltage of the potential divider. If multichip

addressing is not used, connect the ADDR pin to ground.

The chip address is indicated in Bits[2:0] of the 16-bit

command header.

CHIP_ADDR

R/W

BROADCAST

Figure 36. SPI Header Word

HOST

MICROCONTROLLER

SCLK

MISO

MOSI

SCLK

MISO

MOSI

ADE1201

ADDR

SCLK

MISO

MOSI

ADE1201

ADDR

SCLK

MISO

MOSI

ADE1201

ADDR

3.3V

R ±1%

Figure 37. Multichip SPI Addressing Mode

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