ADE1201 datasheet(17/40 Pages) AD

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Data Sheet

ADE1201

Rev. 0 | Page 17 of 40

ADE1201

POWERS UP

2.4V TO 2.6V

3.3V ± 10%

ADE1201

POWERED UP

150ms

320µs

ADE1201

POWER-ON RESET TIMER

TURNED ON

RSTDONE

INTERRUPT

TRIGGERED

ADE1201

READY

MICROPROCESSOR

ACCESSES

ADE1201 SPI

ADDRESS PIN

VALUE SAMPLED

SPI READS BACK AS 0xFFFF

Figure 22. Power-Up Procedure for ADE1201 System

PGA

SAR

ADC

DATA

ISOLATION

DECIMATION

COMPARATOR

DEBOUNCE

DOUT1 PIN

WARNA1

WARNB1

WARNC1

IN1

DOUT1

STATUS,

INT_STATUS

Figure 23. Digital Input Signal Path

DIGITAL INPUTS SIGNAL PATH

A typical ADE1201 application circuit is shown in Figure 20, which

includes external scaling using a voltage divider. The acceptable

input voltage between the IN1 and GNDF pins is given in Table 1.

A full bridge rectifier is required to sense ac signals, as shown in

Figure 20.

Figure 23 shows a detailed view of the digital signal conditioning

done within the ADE1201 IC to generate a DOUT1 digital

output signal based on the input measured on the IN1 pin.

The following sections describe the functionality of each circuit

in detail.

PGA

The PGA stage allows four scaling factors, as shown in Table 14.

The input voltage range is the same as the IN1 input voltage

range (VIN in Table 1 and Table 14). To configure the gain over

the SPI, write to the PGA_GAIN register (Address 0x201),

Bits[1:0] (PGA_GAIN). It is recommended to choose the gain

that maximizes the range of the internal ADC, as shown in

Table 14, without setting the system thresholds outside the range of

the PGA.

By default, the PGA_GAIN bits are cleared to 00, which means

the PGA is set to 1.

Table 14. PGA Gain Settings

VIN

PGA

PGA_GAIN Register, Bits[1:0]

1.25

1×

0.625

2×

0.25

5×

0.125

10×

SAR ADC

After the PGA stage, the ADE1201 SAR ADC produces 8-bit

outputs, as shown in Figure 23. The ADC samples the IN1

channel at 100 kSPS. The digitized data is then passed through

the isolation barrier.

To get an indication of when new ADC samples are ready, write

0x8000 to the MASK register. The IRQ pin goes high for 1 μs

and then low for 9 μs at a rate of 100 kSPS, indicating when new

ADC samples are ready. When reading ADC samples, Bit 15 in the

MASK register, DREADY, must be the only interrupt enabled so

that MASK = 0x8000.

Decimation

The data from the ADC is passed through a decimator. The

decimation filter averages N samples and then decimates by

N, where N is 2, 4, or 8, as configured in the DECRATE bits

(Bits[2:1]) in the BIN_CTRL register (see Table 15). The

decimation filter topology is shown in Figure 24. To enable the

decimation, set Bit 0 (DECIMATE) to 1 in the BIN_CTRL register.

By default, the decimator is disabled and the data from the

ADC bypasses the decimator.

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