ADE1201 datasheet(23/40 Pages) AD

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Data Sheet

ADE1201

Rev. 0 | Page 23 of 40

GATE DRIVE

The GATE pin is used to drive an external high voltage

enhancement mode FET, Q1. After power-up, the GATE pin is

biased at VGATENOM to allow Q1 to conduct the constant current

while protecting the LOAD1 pin, as shown in Figure 34. One

10 Ω, external, gate current limiting resistor (R13), and a 0.1 µF

gate capacitor (C5) are required for stability. Table 1 shows the

nominal VGATENOM voltage (see Figure 34).

During a pulsed current, VGATENOM is regulated to reduce the

voltage on the LOAD1 pin to minimize on-chip power

consumption.

When the external FET is conducting, the corresponding

LOAD1 pin (VGS) is at 0.6 V.

After a pulsed current period, the GATE voltage is regulated

back to VGATENOM. The ADE1201 is compatible with FETs with a

maximum VGS of 6 V.

GATE

IN1

R13

LOAD1

10Ω

0.1µF

ADE1201

GNDF

MOV

275VAC/350VDC

–

10Ω

10nF

VGS

R12

1.1kΩ

1nF

≤300V

95.3kΩ

Figure 34. FET Gate Control

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