ADE1201 datasheet(26/40 Pages) AD

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ADE1201

Data Sheet

Rev. 0 | Page 26 of 40

Each time a register is written, the register value must be

verified by reading it back.

If multiple ADE1201 devices share the same SPI bus (as shown

in Figure 35) and the same register in multiple chips must be

initialized with an identical value, the broadcast write functionality

is available. Set Bit 15 in the SPI header word to 1 to enable a

broadcast write, as shown in Figure 41. Bits[2:0] (CHIP_ADDR) of

the header word that indicate the chip address on the SPI bus

are ignored during a broadcast write.

SPI Read Operation

The registers of the ADE1201 can be read one at a time

following the protocol shown in Figure 39.

A read operation is initiated when the host controller sets the

CS pin low and begins sending a 16-bit command word (see

Figure 36). When the ADE1201 receives the last bit of the

header word, the device begins to transmit the register contents

on the MISO line when the next SCLK high to low transition

occurs. The host controller samples the data on the low to high

SCLK transition.

For an SPI read operation, Bit 3 of the command header must

be set to 1 (see Figure 36).

To ensure the integrity of the SPI read operation, a 16-bit CRC

(CRC-16) of the register value sent out on the MOSI pin can be

included in the transaction. If enabled, the ADE1201 appends

the CRC-16 value during the SPI read operation after the

If Bit 0 (SPI_CRC_APPEND_EN) in the CTRL register is

cleared to 0 (the default value), no CRC value is appended

during an SPI read operation. If the bit is set to 1, the CRC-16

value is appended to the register value read during the SPI read

operation.

The CRC algorithm is based on the standard CRC-16-CCITT

polynomial. The registers are introduced into a linear feedback

shift register (LFSR)-based generator one byte at a time, most

significant byte first, as shown in Figure 42. Each byte is then

used with the MSB first.

Figure 43 shows how the LFSR is used for CRC calculation. The

ADE1201 register forms Bits[a15:a0] used by the LFSR. Bit a0 is

Bit 15 of the register. Bit a15 is Bit 0 of the register.

LFSR GENERATOR

ADE1201

07 8

a15

Figure 42. CRC Calculation

LFSR

a15,a14,...a2,a1,a0

g15

b15

Figure 43. LFSR Generator Used for CRC Calculation

Bits bi(0) = 1, where i = 0, 1, 2, … 15, the initial state of the bits

that form the CRC. Bit b0 is the LSB, and Bit b15 is the MSB.

The coefficients gi, where i = 0, 1, 2, … 15, are the coefficients of

the generating polynomial defined by the CRC-16-CCITT

algorithm as follows:

G(x) = x16 + x12 + x5 + 1

(9)

g0 = g5 = g12 = 1

(10)

All other gi coefficients are equal to 0.

FB(j) = aj − 1 XOR b15(j − 1)

(11)

b0(j) = FB(j) AND g0

(12)

bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, … 15

(13)

Equation 11, Equation 12, and Equation 13 must be repeated for

j = 1, 2, … 16. The value written into the SPI communication CRC

contains Bit bi(16), where i = 0, 1, … 15.

PROTECTING THE INTEGRITY OF CONFIGURATION

REGISTERS

Configuration registers are either user accessible registers (R/W

registers listed in Table 17) or internal registers that are not user

accessible.

On power-up, the user accessible configuration registers can be

written without restriction.

When the registers are configured, write 0xADE1 to the LOCK

side to the nonisolated side. This action also disables write access to

the configuration registers from the SPI port to protect the

integrity of the configuration.

When the protection is enabled, read back the LOCK register to

ensure that Bit 0 (LOCK) was set to 1.

When the LOCK register is read, Bit 0 (LOCK) shows the

protection status. If the LOCK bit is 0, the protection is

disabled. If the LOCK bit is 1, the protection is enabled.

The lock function does not affect the ADDR_RELOAD bit, the

LOCK register, and the INT_STATUS register, which can all be

written when LOCK = 1.

To disable the register protection, write 0xADE0 to the

LOCK register.

To change any configuration registers, disable the protection,

change the value of the register, and then reenable the protection.

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