ADE1201 datasheet(28/40 Pages) AD

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ADE1201

Data Sheet

Rev. 0 | Page 28 of 40

LAYOUT GUIDELINES

Figure 20 shows the schematic of the typical ADE1201

application circuit.

A 4-layer PCB is recommended for the application circuit.

Figure 45 shows the recommended layout to interface one

digital input channel given on P0 with one ADE1201. Do not tie

the GNDF pins from multiple ADE1201 application circuits

together if ac or negative dc inputs are applied.

Figure 45. ADE1201 Circuit Board, Top Layer

Figure 46 shows a close up of the Figure 45 layout, focusing on

the critical areas around the ADE1201.

Figure 46. Close Up of the ADE1201 Support Circuitry

FERRITE BEAD

A ferrite bead is placed on the drain of the FET to prevent

parasitics in the application circuit from resonating with the

FET at high frequencies (hundreds of MHz).

Place a ferrite bead near the drain of the FET (see the yellow

Circle 1 labels in Figure 46).

DECOUPLING AND GROUND PLANE CONNECTION

A low inductance path to the ground plane is required. It is

recommended to use multiple vias to lower the inductance and

provide multiple connections to the GNDF ground pins, Pin 1

and Pin 10.

When placing the decoupling capacitors, ensure that the smaller

capacitor, 0.1 µF, is placed as close as possible to the VDDI pin

and GNDF pin (Pin 10) to provide a low inductance from the

pin to the capacitor, and from the capacitor to ground.

Figure 47 and Figure 48 show close ups of the recommended

layout around the ADE1201 Pin 1 and Pin 10, which are

indicated by the yellow Circle 2 labels in Figure 46.

Figure 47. ADE1201 Pin 1 Close Up

Figure 48. ADE1201 Pin 10 Close Up

Similar rules apply for decoupling on the isolated side for the

GND and VDD supplies on Pin 11 and Pin 12 (see the yellow

Circle 4 label in Figure 46).

Do not tie the GNDF pins from multiple ADE1201 application

circuits together if ac or negative dc inputs are applied.

ELECTOMAGNETIC INTERFACE (EMI) CAPACITOR

High voltage capacitors are recommended to improve emissions

and immunity to conducted disturbances.

These capacitors must be connected between the two ground

planes (GND and GNDF) through multiple vias, as shown in

Figure 49 (see the yellow Circle 3 label in Figure 46).

Take care to meet the application creepage and clearance

requirements because the distance between the ground planes

and the copper on the capacitor footprint is lower than the

creepage and clearance of the ADE1201. Through-hole

capacitors are not recommended.

Figure 49. EMI Capacitor

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