ADE1201 datasheet(13/40 Pages) AD

13 / 40 page

Data Sheet

ADE1201

Rev. 0 | Page 13 of 40

3.0

3.5

4.0

4.5

5.0

5.5

6.0

2.93.0

3.13.23.33.43.5

3.63.7

VDD (V)

Figure 12. IDD vs. VDD

3.0

3.5

4.0

4.5

5.0

5.5

6.0

–50

100

150

TEMPERATURE (°C)

Figure 13. IDD vs. Temperature

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

020

120

100

TIME (ms)

VDD

VLDO

DOUT1

IRQ

Figure 14. Power-Up of Nonisolated Side (VDD, VLDO, DOUT1, and IRQ Pins)

–1

–0.01

0.01

0.03

0.05

0.07

0.09

0.11

0.13

0.15

TIME (Seconds)

VDD

VDDI

VDDL

GATE

Figure 15. Power-Up of Isolated Side (VDDI, VDDL, and GATE Pins) when

VDD Pin is Supplied on Nonisolated Side

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

–1

TIME (ms)

TA = 25°C

VDD = 3.3V

HIGH_CODE = 0x3FF

LOW_CODE = 0x1E

HIGH_TIME = 0xFFF

BIN_FILTER = 0x8096

PL_CTRL = 0

RISE_THR = 0x1E

PROGRAMMABLE

LOAD CURRENT

IN1

DOUT1

–50

100

150

200

250

Figure 16. Typical Input, Digital Output, and Programmable Load Current Signals

(IN1, DOUT1, and Programmable Load Current on Channel 1) in Low Idle Mode

–1

100

150

200

TIME (ms)

IN1

LOAD1

GATE

TA =25°C

VDD = 3.3V

HIGH_CODE = 0x3FF

LOW_CODE = 0x1E

HIGH_TIME = 0xFFF

BIN_FILTER = 0x8096

PL_CTRL = 0

RISE_THR = 0x1E

Figure 17. Typical Input, Gate, and LOAD1 Signals when External FET

Conducting (IN1, Gate, LOAD1)

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ADE1201 数据表(PDF) 13 Page - Analog Devices

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