ADE1201 datasheet(22/40 Pages) AD

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ADE1201

Data Sheet

Rev. 0 | Page 22 of 40

EXTERNAL FET PROTECTION

The external FET protection function monitors the

approximate FET energy based on the programmed load

current and measured digital input voltage over time. When the

accumulation reaches a user programmed limit threshold that is

a function of the programmed current load, the pulsed current

is turned off for a cool down period.

Threshold Calculation

Calculate the expected ADC code for a given input, ADC1, with

the following equation and round to the nearest whole number:

ADC1 = ((Voltage × Gain × Full Scale ADC Codes)/

(Voltage Divider × Reference))

(5)

where:

Voltage is the input voltage to the ADE1201 application circuit

measured in V.

Gain is 1, 2, 5, or 10 according to the setting in the

PGA_GAIN register.

Full Scale ADC Codes is the maximum code output by the ADC,

which is 255.

Voltage Divider is the application circuit voltage divider ratio.

Reference is the voltage reference value, typically 1.25 V,

expressed in V.

Using the safe operating area for the external FET, a threshold,

EGY_MTR_THR, can be calculated to prevent energy from the

pulsed current from exceeding this threshold. To calculate the

threshold, use the following equation:

EGY_MTR_THR = (SOA × ADC1)/(Voltage ×

Pulsed Current × Rate × 27)

(6)

where:

SOA is the energy that can be safely dissipated by the FET,

expressed in J.

Pulsed Current is the pulsed current setting in the

programmable load expressed in A.

Rate is the accumulation rate, 1/100 kHz = 10 µs, expressed in

seconds.

The expected increase for each pulse is given by the following

equation:

Single Pulse Increase = (ADC1 ×

Pulse Current Time)/(Rate × 27)

(7)

When the ADC code is equal to 0xFF in a pulsed current state,

the IN1 input voltage may be greater than the ADC input

voltage range, which can cause the external FET to reach the

limit of the safe operating area more quickly. To model this

effect, configure the OV_SCALE bits in the EGY_MTR_CTRL

energy monitoring accumulation. In this condition, the value of

each pulse can be calculated with the following equation:

(Overvoltage Factor × Full Scale ADC Codes ×

Pulse Current Time)/(Rate × 27)

(8)

where Overvoltage Factor is configured in the OV_SCALE bits in

the EGY_MTR_CTRL register to allow a 1, 4, 8, or 16 scaling

factor.

Cool Down Configuration

When the monitored FET energy reaches the user programmed

energy limit threshold, the pulsed current is turned off for a cool

down period. The cool down period, expressed in seconds, is set in

Bits[3:0] (COOLDOWN_SEC) in the EGY_MTR_CTRL register

(Address 0x015). If the COOLDOWN_SEC bits are cleared to 0,

the cool down functionality is disabled, the load current is not

turned off, and the accumulator is forced to 0.

The external FET energy accumulator is decremented

outside of the pulsed current period by a quantity set in the

COOLDOWN_DECR bits (EGY_MTR_CTRL register,

Bits[15:8]). The decrement frequency is set in the COOLDOWN_

TIMESTEP bits (EGY_MTR_CTRL register, Bits[5:4]). The

frequency can be 10 µs (Bits[5:4] = 00), 20 µs (Bits[5:4] = 01),

40 µs (Bits[5:4] = 10), or 80 µs (Bits[5:4] = 11).

When the ADE1201 is in the cool down period, the

EGY_MTR1 accumulator resets to 0.

The external FET protection function mechanism is shown in

Figure 33.

LOAD

CURRENT

MIN

INPUT

VOLTAGE

TIME

ENERGY

THRESHOLD

FET ENERGY

ACCUMULATOR

DECREMENT DURING

OFF TIME BASED ON

COOLDOWN_DECR AND

COOLDOWN_TIMESTEP

COOLDOWN TIME SET IN

COOLDOWN_SEC.FET

ENERGY ACCUMULATOR RESET

THRESHOLD SET IN

EGY_MTR_THR

OFF

TIME

PROGRAMMED

COOL DOWN

TIME

PROGRAMMED

ENERGY LIMIT

Figure 33. FET Protection Cool Down Feature

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