ADP1034ACPZ-1-R7 datasheet(27/41 Pages) AD

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Data Sheet

ADP1034

THEORY OF OPERATION

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Rev. 0 | 27 of 41

Flyback Regulator Overcurrent Protection

The flyback regulator features a current-limit function that senses

the forward current in the switching metal-oxide semiconductor field

effect transistor (MOSFET) on a cycle by cycle basis. If the current

exceeds the ILIM (FLYBACK) threshold, the switch turns off.

Flyback Regulator Overvoltage Protection

(OVP)

The flyback regulator of the ADP1034 implements a number of

OVP methods to detect and prevent an overvoltage condition on

the flyback regulator output, such as the following:

►

If the voltage on the FB1 pin exceeds VFB1 by 10% for the adjust-

able output version, an OVP fault is detected, which prevents the

flyback regulator switch from turning on. The flyback regulator

primary switch stays off until the OVP condition is no longer

present.

►

If communication across the isolation barrier from the secondary

controller to the primary controller fails, the flyback regulator

shuts down and a new soft start power-up cycle initiates.

►

If the voltage on the output of the flyback regulator exceeds

the severe overvoltage threshold (SOVPFLYBACK), the primary

controller does not turn on the primary side switch. The flyback

regulator primary switch stays off until the voltage on the VOUT1

pin falls below the SOVPFLYBACK − SOVPFLYBACK_HYST threshold.

Flyback Programmable Power Control (PPC)

A PPC_IN pin is provided to allow communications between

the ADP1034 and a microcontroller unit (MCU) for adjusting the

ADP1034 feedback voltage of the flyback regulator (VFB1) through

a serial command. The ADP1034 uses an exclusive, proprietary

intellectual property 1-wire serial interface protocol. This communi-

cations protocol is designed such that an MCU (or a companion

product) acts as the master while the ADP1034 acts as the slave

when configuring the output settings of the flyback regulator. The

MCU actively determines if the power needs of its load changes

before triggering an on demand request to the ADP1034 to adjust

its output voltage to meet the power needs of the load.

During startup and when programming the flyback output (VOUT1)

below 4.5 V, the PPC interface puts the flyback regulator in its

default state of PPC Code 251. PPC Code 252 to Code 255 are

reserved for factory trimming purposes and are clamped to Code

251 when written.

1-Wire Serial Interface

PPC is implemented via a 1-wire serial interface in the ADP1034.

An OWSI transaction requires several elements, as shown in Figure

77. The OWSI frame is broken into bit periods. Each start event,

data bit, and acknowledge bit occur within a bit period, and each

timing specification is defined from the start of that bit period.

A start sequence is defined by two successive rising edge pulses.

After the start command is transmitted, 16 data bits follow to make

up the address (default = 000), data, and CRC bits (MSB first).

Finally, an acknowledge sequence is required from the slave. The

acknowledge is composed of two bits: an acknowledge bit (ACK in

Figure 77) and a parity bit.

The MCU pulls the 1-wire serial interface bus high at the start of

the acknowledge and parity bit periods. The 1-wire serial interface

bus is sampled by the MCU for a fixed time during the acknowledge

and parity bit periods. At this time, the slave may drive the bus low.

If the slave does not pull the bus low, the MCU drives low later

in the acknowledge and parity bit periods. Refer to Figure 2 for a

detailed view of the 1-wire serial interface timing and Table 2 for the

appropriate timing specifications.

In a successful transaction, the slave remains high during the

acknowledge bit period and drives the bus low during the parity bit

period. In an unsuccessful transaction, the slave drives the bus low

during the acknowledge bit and remains high during the parity bit

period.

1-Wire Serial Interface CRC

To ensure that data is received correctly in noisy environments,

a cyclic redundancy check (CRC) is implemented in the 1-wire

serial interface. This CRC is based on a 5-bit frame with the check

sequence using the following polynomial:

C(x) = x5 + x2 + 1

This 5-bit frame check sequence is added to the end of the 11-bit

data-word, and the full 16-bit word is sent by the MCU to the

ADP1034. Then the MCU expects an acknowledge sequence from

the ADP1034. If the corresponding CRC check on the ADP1034

is valid, the ADP1034 responds with an acknowledge sequence,

which means that a write was completed. Then, the flyback output,

VOUT1, of the ADP1034 is adjusted according to the 8-bit data writ-

ten. If the CRC on the ADP1034 is not valid, the no acknowledge

sequence is issued, and the data is ignored. Then, the flyback

output, VOUT1, does not change.

Figure 77. 1-Wire Serial Interface Write with Acknowledge

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