ADP1034ACPZ-1-R7 datasheet(29/41 Pages) AD

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Data Sheet

ADP1034

THEORY OF OPERATION

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peak inductor current to ILIM (INVERTER), resulting in a drop in the

output voltage.

Inverting Regulator OVP

The inverting, dc-to-dc regulator of the ADP1034 features an OVP

circuit that monitors the voltage on the FB3 pin. If the voltage

on this pin falls below VFB3 by 10%, the inverting regulator stops

switching until the voltage rises above the threshold again.

Inverting Regulator Active Pull-Down Resistor

The inverting regulator has an active pull-down resistor that dis-

charges the output capacitor when the output of VOUT1 is between

1.23 V and 4.5 V. The pull-down resistor connects between VOUT3

and SGND2.

POWER-UP SEQUENCE

The power-up sequence is shown in Figure 78.

1. The flyback regulator powers up first.

2. When VOUT1 rises above 90% of the target VOUT1, the buck

regulator turns on.

3. When the buck regulator output (VOUT2) rises above 90% of the

target VOUT2, the inverting regulator turns on.

Figure 78. Power-Up Sequencing

OSCILLATOR AND SYNCHRONIZATION

A phase-locked loop (PLL)-based oscillator generates the internal

clock for the flyback, buck, and inverter regulators, and offers an

internally generated frequency or external clock synchronization.

Connect the SYNC pin as described in Table 13 to configure the

switching frequency, fSW. For external synchronization, connect the

SYNC pin to a suitable clock source. The PLL locks to an input

clock within the range specified by fSYNC.

Table 13. SYNC Pin Functionality

SYNC Pin State and Frequency

Flyback fSW Buck fSW

Inverter fSW

SYNC Pin State: Low or High

250 kHz

125 kHz

fSYNC: 350 kHz to 750 kHz

fSYNC ÷ 2

fSYNC ÷ 4

THERMAL SHUTDOWN

If the ADP1034 junction temperature rises above TSHDN, the ther-

mal shutdown circuit turns the flyback regulator off. Extreme junc-

tion temperatures can be the result of prolonged high current opera-

tion, poor circuit board design, and/or high ambient temperatures.

When thermal shutdown occurs, hysteresis is included so that the

ADP1034 does not return to operation until the on-chip temperature

drops below TSHDN − THYS. When resuming from thermal shutdown,

the ADP1034 performs a soft start.

DATA ISOLATION

High Speed SPI Channels

The ADP1034 has four high speed channels. The first three, CLK,

MI/SO, and MO/SI (the slash indicates the connection of the input

and output, forming a datapath across the isolator that corresponds

to an SPI bus signal) are optimized for low propagation delay. With

a maximum propagation delay of 15 ns, the ADP1034 supports

read and write clock rates up to 16.6 MHz in the standard 4-wire

SPI. However, the total round trip delay of the system determines

the maximum clock rate and is less than that value.

The relationship between the SPI signal paths, the ADP1034 pin

mnemonics, and the data directions are detailed in Table 14.

Table 14. Relationship Between Pin Mnemonics and SPI Signal Path Names

SPI Signal Path

Master Side

Data Direction

Slave Side

Clock (CLK)

MCK

→

SCK

MO/SI

→

MI/SO

←

Slave Select Bar (SS)

MSS

→

SSS

The datapaths are SPI mode agnostic. The CLK and MO/SI SPI

datapaths are optimized for propagation delay and channel to chan-

nel matching. The MI/SO SPI datapath is optimized for propagation

delay. The device does not synchronize to the clock channels.

Therefore, there are no constraints on the clock polarity or timing

with respect to the data lines.

SS is an active low signal. To save power in a multichannel system,

SS puts the other SPI isolator channels in a low power state when

the channels are not in use (SS = high), and these channels are

only active when required, which is when SS is low. The clock and

data channels are gated to the SS as shown in Figure 79. However,

this power saving mode adds 100 ns of latency. This latency is

the time required for the internal circuitry to wake up from the low

power state and to start transmitting data to the isolation barrier.

Conversely, the latency is the delay from the falling edge of MSS to

the first clock edge or data edge that appears on the slave side, as

shown in Figure 80.

Figure 79. iCoupler Gating

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