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ADP1034ACPZ-1-R7 数据表(PDF) 12 Page - Analog Devices |
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ADP1034ACPZ-1-R7 数据表(HTML) 12 Page - Analog Devices |
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12 / 41 page  Data Sheet ADP1034 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS analog.com Rev. 0 | 12 of 41 Table 11. Pin Function Descriptions Pin No. Mnemonic Isolation Domain Direction Description 23 SGPI1 Slave Input General-Purpose Input 1. This pin is paired with MGPO1. 24 PPC_IN Slave Input Programmable Power Control Input. Single pin access for PPC communication for adjusting VOUT1 setting through a serial command. 25 DNC Slave Do not connect. Do not connect to this pin. 26 DNC Slave Do not connect. Do not connect to this pin. 27 SGND2 Slave Ground Slave Domain Ground Connection. This pin can be left unconnected. 28 PGNDP Field power Ground Ground Return for Flyback Regulator Power Supply. 29 SWP Field power Flyback Regulator Switching Node. Primary side transformer connection. 30 VINP Field power Power Flyback Regulator Supply Voltage. Connect a minimum of 3.3 µF capacitor from VINP to PGNDP. 31 EN Field power Input Precision Enable. Compare the EN pin to an internal precision reference to enable the flyback regulator output. Use a resistor divider that is between 10 kΩ and 1 MΩ. 32 SLEW Field power Input Flyback Regulator Slew Rate Control. The SLEW pin sets the slew rate for the SWP driver. For the fastest slew rate (best efficiency), leave the SLEW pin open. For the normal slew rate, connect the SLEW pin to VINP. For the slowest slew rate (lowest EMI), connect the SLEW pin to GNDP. 33 GNDP Field power Ground Field Power Signal Ground Connection. 34 MGND Master Ground Master Domain Power Ground Connection. 35 MGPO1 Master Output General-Purpose Output 1. This pin is paired with SGPI1. 36 MGND Master Ground Master Domain Power Ground Connection. 37 MGPI2 Master Input General-Purpose Input 2. This pin is paired with SGPO2. 38 MGPO3 Master Output General-Purpose Output 3. This pin is paired with SGPI3. 39 MVDD Master Power Master Domain Power. Connect a 100 nF decoupling capacitor from MVDD to MGND. 40 MCK Master Input SPI Clock Input from the Master Controller. Paired with SCK. On the slave domain, this pin drives SCK. 41 MO Master Input SPI Data Input Going to Slave MO and SI Line. Paired with SI. On the slave domain, this pin drives SI. EPGNDP Field power Ground PGNDP Exposed Pad. This pad is internally connected to PGNDP. EPGNDM Master Ground MGND Exposed Pad. This pad is internally connected to MGND. EPGND2 Slave Ground SGND Exposed Pad. This pad is internally connected to SGNDx. |
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