ADP1034ACPZ-1-R7 datasheet(40/41 Pages) AD

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Data Sheet

ADP1034

PCB LAYOUT CONSIDERATIONS

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Rev. 0 | 40 of 41

To achieve optimum efficiency, proper regulation, strong stability,

and proper PPC operation, a well designed PCB layout is required.

Follow these guidelines when designing PCBs:

►

Keep the input bypass capacitor, CIN, close to the VINP pin, and

the PGNDP pin.

►

Keep the high current paths as short and wide as possible to

minimize parasitic series inductance, which causes spiking and

EMI. These paths include the connections between the following:

►

CIN, VINP, transformer primary, and PGNDP

►

VOUT1, CFLYBK, D1, transformer secondary, and SGND2

►

VOUT2, SW2, L1, CBUCK, and SGND2

►

VOUT3, SW3, L2, CINV, and SGND2

►

Avoid routing high impedance traces like feedback and PPC_IN

traces near or directly under any of the high current switching

paths to prevent radiated switching noise injection.

►

Place the feedback resistors as close to the FB1 and FB3 pins

as possible to prevent high frequency switching noise injection.

►

To minimize EMI, place the MVDD decoupling capacitor (C1)

close to MVDD (Pin 39) and MGND (Pin 3).

►

To minimize EMI, place the SVDD1 decoupling capacitor (C3)

close to SVDD1 (Pin 10) and SGND1 (Pin 5), and place the

SVDD2 decoupling capacitor (C7) close to SVDD2 (Pin 20) and

SGND2 (Pin 16).

Figure 90 shows a suggested top layer layout for the ADP1034.

Figure 90. Suggested ADP1034 Top Layer Layout

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