ADP1034ACPZ-1-R7 datasheet(10/41 Pages) AD

10 / 41 page

Data Sheet

ADP1034

ABSOLUTE MAXIMUM RATINGS

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Rev. 0 | 10 of 41

Table 7.

Parameter

Rating

VINP to PGNDP

61 V

SWP to PGNDP

VINP + 70 V or 110 V, whichever is lower

SWP to VINP

110 V – VINP or 70 V, whichever is lower

SLEW to GNDP

−0.3 V to VINP + 0.3 V

EN to GNDP

−0.3 V to +61 V

VOUT1 to SGND2

35 V

FB1 to SGND2

−0.3 V to +3.3V

VOUT1 to VOUT3

61 V

SW2 to SGND2

−0.3 V to VOUT1 + 0.3 V

VOUT2 to SGND2

6 V

SW3 to SGND2

VOUT3 − 0.3 V to VOUT1 + 0.3 V

VOUT3 to SGND2

−26 V to +0.3 V

FB3 to VOUT3

−0.3 V to +3.3V

SVDD1 to SGND1

6.0 V

SVDD2 to SGND2

6.0 V

SSS, SCK, SI, SO to SGND1

−0.3 V to SVDD1 + 0.3 V

SGPI1, SGPO2, SGPI3 to SGND2

−0.3 V to SVDD2 + 0.3 V

SYNC to SGND2

−0.3 V to +6 V

PPC_IN to SGND2

−0.3 V to +6 V

MVDD to MGND

6.0 V

MSS, MCK, MO, MI to MGND

−0.3 V to MVDD + 0.3 V

MGPO1, MGPI2, MGPO3 to MGND

−0.3 V to MVDD + 0.3 V

Common-Mode Transients

±100 kV/μs

Operating Junction Temperature

Range1

−40°C to +125°C

Storage Temperature Range

−65°C to +150°C

Lead Temperature

JEDEC industry standard

Soldering Conditions

JEDEC J-STD-020

1 Power dissipated on chip must be derated to keep the junction temperature

below 125°C.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress

rating only; functional operation of the device at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum operat-

ing conditions for extended periods may affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to PCB

thermal design is required.

θJA is the natural convection, junction to ambient thermal resistance

measured in a one cubic foot sealed enclosure. θJC is measured

at the top of the package and is independent of the PCB. The ΨJT

value is appropriate for calculating junction to case temperature in

the application.

Table 8. Thermal Resistance

Package Type

θJA

θJC

ψJT

Unit

CP-41-11, 2, 3

50.4

33.1

°C/W

1 9 mm × 7 mm LFCSP with omitted pins for isolation purposes.

2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board with 19 thermal vias. See JEDEC JESD-51.

3 Case temperature was measured at the center of the package.

ELECTROSTATIC DISCHARGE (ESD) RATINGS

The following ESD information is provided for handling of ESD-sen-

sitive devices in an ESD protected area only.

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Field induced charged device model (FICDM) and charged device

model (CDM) per ANSI/ESDA/JEDEC JS-002.

ESD Ratings for ADP1034

Table 9. ADP1034, 41-Lead LFCSP

ESD Model

Withstand Threshold (V)

Class

HBM

3500

FICDM

1250

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devi-

ces and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

MAXIMUM CONTINUOUS WORKING VOLTAGE

Table 10. Maximum Continuous Working Voltage1

Parameter

Value

Constraint

60 Hz AC Voltage

300 V rms

20-year lifetime at 0.1% failure rate, zero average voltage

DC Voltage

424 V peak

Limited by the creepage of the package, Pollution Degree 2, Material Group II2, 3

1 See the Insulation Lifetime section for more details.

2 Other pollution degree and material group requirements yield a different limit.

3 Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards.

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