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ADP1034ACPZ-1-R7 数据表(PDF) 6 Page - Analog Devices |
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ADP1034ACPZ-1-R7 数据表(HTML) 6 Page - Analog Devices |
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6 / 41 page  Data Sheet ADP1034 SPECIFICATIONS analog.com Rev. 0 | 6 of 41 Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Logic High VOH VxVDD − 0.1 V IOx4 = −20 µA, VIx = VIxH5 VxVDD − 0.4 V IOx4 = −2 mA, VIx = VIxH5 Logic Low VOL 0.0 0.1 V IOx4 = 20 µA, VIx = VIxL6 0.2 0.4 V IOx4 = 2 mA, VIx = VIxL6 MGPO1, SGPO2, MGPO3 Output Voltage Logic High VOH VxVDD − V IOx4 = −20 µA, VIx = VIxH5 0.1 VxVDD − V IOx4 = −500 µA, VIx = VIxH5 0.4 Logic Low VOL 0.1 V IOx4 = 20 µA, VIx = VIxL6 0.15 0.4 V IOx4 = 500 µA, VIx = VIxL6 SCK, SI, MI Tristate Leakage −1 +0.01 +1 μA MSS = logic high −1 +0.01 +1 μA VOx7 = VxVDD ISOLATORS SWITCHING SPECIFICATION MCK, MSS, MO, SO SPI Clock Rate SPIMCK 16.6 MHz Latency 100 125 ns Delay from MSS going low to the first data output is valid Input Pulse Width tPW 17 ns Within PWD limit Input Pulse Width Distortion (PWD) tPWD 0.25 6.5 ns |tPLH − tPHL| Channel Matching Codirectional tPSKCD 0.5 5.5 ns Opposing Direction tPSKOD 0.5 4 ns Propagation Delay tPHL, tPLH 50% input to 50% output 7 11 ns VMVDD = 5 V, VSVDD1 = 5 V 7 12 ns VMVDD = 3.3 V, VSVDD1 = 5 V 7 15 ns VMVDD = 3.3 V, VSVDD1 = 3.3 V 8.5 12 ns VMVDD = 2.3 V, VSVDD1 = 1.8 V Jitter 620 ps p-p VMVDD = 5 V, VSVDD1 = 5 V 100 ps rms VMVDD = 5 V, VSVDD1 = 5 V 440 ps p-p VMVDD = 3.3 V, VSVDD1 = 5 V 80 ps rms VMVDD = 3.3 V, VSVDD1 = 5 V 290 ps p-p VMVDD = 3.3 V, VSVDD1 = 3.3 V 60 ps rms VMVDD = 3.3 V, VSVDD1 = 3.3 V 410 ps p-p VMVDD = 2.3 V, VSVDD1 = 1.8 V 110 ps rms VMVDD = 2.3 V, VSVDD1 = 1.8 V SGPI1, MGPI2, SGPI3 Data Rate 100 kbps Input Pulse Width tPW 10 µs Within PWD limit Propagation Delay tPHL, tPLH 14 µs 50% input to 50% output Jitter 10 µs ISOLATORS AC SPECIFICATIONS General-Purpose Input/Output (GPIO) Output Rise Time/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient Immunity8 |CM| 25 kV/µs |
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