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9.2 Peripheral- and Interface-Specific Design Information

9.2.1 General Routing Guidelines

The following paragraphs detail the routing guidelines that must be observed when routing the various functional

LVCMOS interfaces.

• Line spacing:

– For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the

crosstalk between switching signals between the different lines. On the PCB, this is not achievable

everywhere (for example, when breaking signals out from the device package), but it is recommended

to follow this rule as much as possible. When violating this guideline, minimize the length of the traces

running parallel to each other (see Figure 9-1).

D+

S = 2 W = 200 µm

SWPS040-185

Figure 9-1. Ground Guard Illustration

• Length matching (unless otherwise specified):

– For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length difference

between the longest and the shortest lines) must be less than 25 mm.

– For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length

difference between the longest and the shortest lines) must be less than 2.5 mm.

• Characteristic impedance

– Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to

be between 35-Ω and 65-Ω.

• Multiple peripheral support

– For interfaces where multiple peripherals have to be supported in the star topology, the length of each

branch has to be balanced. Before closing the PCB design, it is highly recommended to verify signal

integrity based on simulations including actual PCB extraction.

9.2.2 DDR Board Design and Layout Guidelines

The goal of the AM64x\AM243x DDR Board Design and Layout Guidelines is to make the DDR system

implementation straightforward for all designers. Requirements have been distilled down to a set of layout and

routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.

TI only supports board designs using DDR4 or LPDDR4 memories that follow the guidelines in this document.

www.ti.com

AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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