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• One controller with 8-bit wide data bus

• One controller with 4-bit wide data bus

• Support of eMMC5.1 Host Specification (JESD84-B51)

• Support of SD Host Controller Standard Specification - SDIO 3.00

• Integrated DMA controller supporting SD Advanced DMA - ADMA2 and ADMA3

• eMMC Electrical Standard 5.1 (JESD84-B51)

• Multi-Media card features:

– Backward compatible with earlier eMMC standards

– Legacy MMC SDR: 1.8 V, 8/4/1-bit bus width, 0-25 MHz, 25/12.5/3.125 MB/s

– High Speed SDR: 1.8 V, 8/4/1-bit bus width, 0-50 MHz, 50/25/6.25 MB/s

– High Speed DDR: 1.8 V, 8/4-bit bus width, 0-50 MHz, 100/50 MB/s

– HS200 SDR: 1.8 V, 0-200 MHz, 8/4-bit bus width, 200/100 MB/s

• SD card support: SDIO, SDR12, SDR25, SDR50, DDR50

• System bus interface: CBA 4.0 VBUSM initiator port with 64-bit data width and 64-bit address, little Endian

only

• Configuration bus interface: CBA 4.0 VBUSM with 32-bit data width, 32-bit aligned accesses only, linear

incrementing addressing mode, little Endian only

For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in

the device TRM.

8.4.2.16 OSPI

The Octal Serial Peripheral Interface (OSPI) module is a kind of Serial Peripheral Interface (SPI) module which

allows single, dual, quad or octal read and write access to external flash devices. This module has a memory

mapped register interface, which provides a direct memory interface for accessing data from external flash

devices, simplifying software requirements.

The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor

wishing to execute code directly from external flash memory), or in an indirect mode where the module is

set-up to silently perform some requested operation, signaling its completion via interrupts or status registers.

For indirect operations, data is transferred between system memory and external flash memory via an internal

SRAM which is loaded for writes and unloaded for reads by a device controller at low latency system speeds.

Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using

user programmable configuration registers.

For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device

TRM.

8.4.2.17 Peripheral Component Interconnect Express (PCIe)

The PCIe subsystem supports the following main features:

• Dual mode – root port (RP) or end point (EP) modes. Selectable through bootstrap pins.

• 1-lane configuration with up to 5.0GT/lane.

• 62.5/125 MHz operation on PIPE interface for Gen1/Gen2 respectively

• Constant 32-bit PIPE width for Gen1/Gen2 modes

• Maximum outbound payload size of 128 bytes

• Maximum inbound payload size of 128 bytes

• Maximum remote read request size of 4K bytes

• Maximum number of nonposted outstanding transactions: 8 on each VBUSM interface.

• Four virtual channels (4VC)

• Resizable BAR capability

• SRIS support

• Power Management

– L1 Power Management Substate support

– D1 support

– L1 Power Shutoff support

• Legacy, MSI, and MSI-X interrupt support

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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