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These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction for most encoders

is defined as the QEPA channel going positive before the QEPB channel and vice versa.

The encoder wheel typically makes one revolution for every revolution of the motor or the wheel can be at a

geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from the

QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder

directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6 KHz, so

by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the

motor.

For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter

in the device TRM.

8.4.2.10 GPMC

The GPMC module supports the following features:

• Data path to external memory device can be 32, 16 or 8 bits wide

• Support for the following memory types:

– Asynchronous or synchronous 8-bit memory or device (non-burst device)

– Asynchronous or synchronous 16-bit memory or device

– Asynchronous or synchronous 32-bit memory or device

– 16-bit non-multiplexed NOR Flash device

– 16-bit address and 32-bit address and data multiplexed NOR Flash device

– 8-bit and 16-bit NAND flash device

– 16-bit and 32bit pSRAM device

• Supports Error Code detection using BCH code (t=4, 8 or 16) or Hamming code for 8-bit or 16-bit NAND-

flash, organized with page size of 512 Byte, 1Kbytes, or more. • Supports 1 GByte maximum addressing

capability, which can be divided into 8 independent chip-select with programmable bank size and base

address on 16 MByte, 32 MByte, 64 MByte, or 128 MByte boundary.

• Fully-pipelined operation for optimal memory bandwidth usage

• Supports external device clock frequency of /1, /2, /3, and /4 divide of interface clock

• Supports programmable auto-clock gating when there is no access

• Supports MIdlereq/SIdleAck protocol

• Supports the following interface protocols when communicating with external memory or external devices:

– Asynchronous read/write access

– Asynchronous read page access (4-8-16 Word16), 4-8-16 Word32

– Synchronous read/write access

– Synchronous read burst access without wrap capability (4-8-16-32 Word16, 4-8-16 Word32)

– Synchronous read burst access with wrap capability (4-8-16-32 Word16, 4-8-16 Word32)

• Address and data multiplexed access

• Each chip-select has independent and programmable control signal timing parameters for Setup and Hold

time. Parameters are set according to the memory device timing parameters, with one interface clock cycle

timing granularity.

• Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin

• Supports bus keeping

• Supports bus turn around

• Pre-fetch and write posting engine associated with system DMA, to get full performance from NAND device,

and with minimum impact on NOR/SRAM concurrent access monitoring (up to 4 WAIT pins)

For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the

device TRM.

8.4.2.11 I2C

The Inter-IC Bus (I2C) interface is implemented using the mshsi2c module. This peripheral implements the

multi-controller I2C bus, which allows serial transfer of 8-bit data to and from other I2C controller and target

devices, through a two-wire interface.

The I2C module supports the following main features:

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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