AM2434...ALV datasheet(247/280 Pages) TI

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8.2 Processor Subsystems

8.2.1 Arm Cortex-R5F Subsystem (R5FSS)

The R5FSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for dual/single-core

operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®

CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and

various wrappers for protocol conversion and address translation for easy integration into the SoC.

Note

The Cortex®-R5F processor is a Cortex-R5 processor that includes the optional Floating Point Unit

(FPU) extension.

For more information, see Dual-R5F Subsystem (R5FSS) section in Processors and Accelerators chapter in the

device TRM.

8.2.2 Arm Cortex-M4F (M4FSS)

The M4FSS module on the AM243x device provides a safety channel (secondary channel - working in

conjunction with an external microcontroller)- or- a general purpose MCU.

The M4FSS module supports the following features:

• Cortex M4F With MPU

• ARMv7-M architecture

• Support for Nested Vectored Interrupt Controller (NVIC) with 64 inputs

• Ability to executed code from internal or external memories

• 192 KB of SRAM (I-Code)

• 64 KB of SRAM (D-Code)

• External access to internal memories if allowed

• Debug Support Including:

– DAP based Debug to the CPU Core

– Full Debug Features of CPU Core are enabled

– Standard ITM trace

– CTM Cross Trigger

– ETM Trace Support

• Fault Detection and Correction

– SECDED ECC protection on I-CODE

– SECDED ECC protection on D-CODE

– Fault Error Interrupt Output

For more information, see Arm Cortex M4F Subsystem (M4FSS) section in Processors and Accelerators chapter

in the device TRM.

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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