数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

AM2434...ALV 数据表(PDF) 244 Page - Texas Instruments

部件名 AM2434...ALV
功能描述  AM243x Sitara™ Microcontrollers
PDF  280 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM2434...ALV 数据表(HTML) 244 Page - Texas Instruments

Back Button AM2434...ALV Datasheet HTML 240Page - Texas Instruments AM2434...ALV Datasheet HTML 241Page - Texas Instruments AM2434...ALV Datasheet HTML 242Page - Texas Instruments AM2434...ALV Datasheet HTML 243Page - Texas Instruments AM2434...ALV Datasheet HTML 244Page - Texas Instruments AM2434...ALV Datasheet HTML 245Page - Texas Instruments AM2434...ALV Datasheet HTML 246Page - Texas Instruments AM2434...ALV Datasheet HTML 247Page - Texas Instruments AM2434...ALV Datasheet HTML 248Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 244 / 280 page
background image
7.10.6 Emulation and Debug
For more details about features and additional description information on the device Trace and JTAG interfaces,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.10.6.1 Trace
Table 7-146. Trace Timing Conditions
PARAMETER
MIN
MAX
UNIT
OUTPUT CONDITIONS
CL
Output load capacitance
2
5
pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch)
Propagation delay mismatch across all traces
VDDSHV3 = 1.8V
200
ps
VDDSHV3 =3.3V
100
ps
Table 7-147. Trace Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
1.8V Mode
DBTR1
tc(TRC_CLK)
Cycle time, TRC_CLK
6.50
ns
DBTR2
tw(TRC_CLKH)
Pulse width, TRC_CLK high
2.50
ns
DBTR3
tw(TRC_CLKL)
Pulse width, TRC_CLK low
2.50
ns
DBTR4
tosu(TRC_DATAV-
TRC_CLK)
Output setup time, TRC_DATA valid to TRC_CLK edge
0.81
ns
DBTR5
toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
0.81
ns
DBTR6
tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
0.81
ns
DBTR7
toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
0.81
ns
3.3V Mode
DBTR1
tc(TRC_CLK)
Cycle time, TRC_CLK
8.67
ns
DBTR2
tw(TRC_CLKH)
Pulse width, TRC_CLK high
3.58
ns
DBTR3
tw(TRC_CLKL)
Pulse width, TRC_CLK low
3.58
ns
DBTR4
tosu(TRC_DATAV-
TRC_CLK)
Output setup time, TRC_DATA valid to TRC_CLK edge
1.08
ns
DBTR5
toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
1.08
ns
DBTR6
tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
1.08
ns
DBTR7
toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
1.08
ns
TRC_DATA
TRC_CTL
TRC_CLK
(
)
(
)
(Ideal)
Worst Case 1
Worst Case 2
DBTR1
DBTR2
DBTR3
DBTR4
DBTR6
DBTR5
DBTR7
DBTR4
DBTR6
DBTR5
DBTR7
SPRSP08_Debug_01
Figure 7-115. Trace Switching Characteristics
AM2434, AM2432, AM2431
SPRSP65D – APRIL 2021 – REVISED AUGUST 2022
www.ti.com
244
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: AM2434 AM2432 AM2431



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com