| 数据搜索系统,热门电子元器件搜索 |
|
AM2434...ALV 数据表(PDF) 105 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM2434...ALV 数据表(HTML) 105 Page - Texas Instruments |
|
105 / 280 page ![]() Table 6-69. Sysboot Signal Descriptions (continued) Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] BOOTMODE13 I Bootmode pin 13 V18 Y19 BOOTMODE14 I Bootmode pin 14 Y21 Y18 BOOTMODE15 I Bootmode pin 15 Y20 AA19 6.3.22.2 Clocking MCU Domain Instances Table 6-70. MCU Clock Signal Descriptions Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] MCU_OSC0_XI I High frequency oscillator input C21 D20 MCU_OSC0_XO O High frequency oscillator output B20 C21 6.3.22.3 SYSTEM MAIN Domain Instances Table 6-71. System Signal Descriptions Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] CLKOUT0 O RMII Clock Output (50 MHz). This pin is used for Clock source to the external PHY and must be routed back to the RMII_REF_CLK pin for proper device operation. A19, U13 A18, V13 EXTINTn (2) (3) I External Interrupt C19 EXT_REFCLK1 I External Clock input to MAIN domain, routed to Timer Clock muxes as one of the selectable input Clock sources for Timer/WWDT modules, or as reference Clock to MAIN_PLL2 (PER1 PLL) A19 A18 GPMC0_FCLK_MUX (1) O GPMC functional Clock output selected through mux logic R17 OBSCLK0 O Observation Clock output for test and debug purposes only D17 A15 PORz_OUT O MAIN domain POR status output E17 D18 RESETSTATz O MAIN domain warm reset status output F16 E19 RESET_REQz I MAIN domain external warm reset request input E18 C17 SYSCLKOUT0 O SYSCLK0 output from MAIN PLL controller (divided by 6) for test and debug purposes only C17 B14 (1) The GPMC0_FCLK_MUX signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. (2) The EXTINTn signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. (3) EXTINTn is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer. MCU Domain Instances Table 6-72. MCU System Signal Descriptions Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] MCU_EXT_REFCLK0 (2) I External system Clock input B7 MCU_OBSCLK0 O Observation Clock output for test and debug purposes only C6, E10 B3 MCU_PORz I MCU domain cold reset B21 C20 MCU_RESETSTATz O MCU domain warm reset status output B13 A6 MCU_RESETz I MCU domain warm reset B12 A5 MCU_SAFETY_ERRORn IO Error signal output from MCU domain ESM A20 B20 MCU_SYSCLKOUT0 (1) O MCU domain system Clock output for test and debug purposes only C6 (1) The MCU_SYSCLKOUT0 signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. www.ti.com AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 105 Product Folder Links: AM2434 AM2432 AM2431 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |