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AM2434...ALV 数据表(PDF) 109 Page - Texas Instruments |
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AM2434...ALV 数据表(HTML) 109 Page - Texas Instruments |
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109 / 280 page  6.4 Pin Connectivity Requirements This section describes connectivity requirements for package balls that have specific connectivity requirements and unused package balls. Note All power balls must be supplied with the voltages specified in the Recommended Operating Conditions section, unless otherwise specified in Signal Descriptions. Note For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball numbers. Table 6-86. Connectivity Requirements (ALV Package) BALL NUMBER BALL NAME CONNECTION REQUIREMENTS A20 D11 MCU_SAFETY_ERRORn TRSTn Each of these balls must be connected to VSS through separate external pull resistors to ensure these balls are held to a valid logic low level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-down can be used to hold a valid logic low level if no PCB signal trace is connected to the ball. D10 E10 B12 E18 B11 C11 C12 EMU0 EMU1 MCU_RESETz RESET_REQz TCK TDI TMS Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure these balls are held to a valid logic high level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-up can be used to hold a valid logic high level if no PCB signal trace is connected to the ball. A18 B18 E9 A10 I2C0_SCL I2C0_SDA MCU_I2C0_SCL MCU_I2C0_SDA Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure these balls are held to a valid logic high level. T20 U21 T18 U20 U18 U19 V20 V21 V19 T17 R16 W20 W21 V18 Y21 Y20 GPMC0_AD0 GPMC0_AD1 GPMC0_AD2 GPMC0_AD3 GPMC0_AD4 GPMC0_AD5 GPMC0_AD6 GPMC0_AD7 GPMC0_AD8 GPMC0_AD9 GPMC0_AD10 GPMC0_AD11 GPMC0_AD12 GPMC0_AD13 GPMC0_AD14 GPMC0_AD15 Each of these balls must be connected to the corresponding power supply(1) or VSS through separate external pull resistors to ensure these balls are held to a valid logic high or low level as appropriate to select the desired device boot mode. J13 G20 F20 E21, D20 G21 F21 F19 E20 J15 J16 VDDA_ADC ADC0_AIN0 ADC0_AIN1 ADC0_AIN2 ADC0_AIN3 ADC0_AIN4 ADC0_AIN5 ADC0_AIN6 ADC0_AIN7 ADC0_REFP ADC0_REFN If the entire ADC0 is not used, each of these balls must be connected directly to VSS. www.ti.com AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: AM2434 AM2432 AM2431 |
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