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AM2434...ALV 数据表(PDF) 201 Page - Texas Instruments |
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AM2434...ALV 数据表(HTML) 201 Page - Texas Instruments |
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201 / 280 page  7.10.5.12.2 MMC1 - SD/SDIO Interface MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications: • Default speed • High speed • UHS–I SDR12 • UHS–I SDR25 • UHS–I SDR50 • UHS–I SDR104 • UHS–I DDR50 Table 7-75 presents the required DLL software configuration settings for MMC1 timing modes. Table 7-75. MMC1 DLL Delay Mapping for all Timing Modes REGISTER NAME MMCSD1_SS_PHY_CTRL_4_REG MMCSD1_SS_PHY_CTRL_5_REG BIT FIELD [20] [15:12] [8] [4:0] [2:0] BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL MODE DESCRIPTION DELAY ENABLE DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DELAY BUFFER DURATION Default Speed 4-bit PHY operating 3.3 V, 25 MHz 0x0 0x0 0x1 0x0 0x7 High Speed 4-bit PHY operating 3.3 V, 50 MHz 0x0 0x0 0x1 0x0 0x7 UHS-I SDR12 4-bit PHY operating 1.8 V, 25 MHz 0x1 0xF 0x1 0x0 0x7 UHS-I SDR25 4-bit PHY operating 1.8 V, 50 MHz 0x1 0xF 0x1 0x0 0x7 UHS-I SDR50 4-bit PHY operating 1.8 V, 100 MHz 0x1 0xC 0x1 Tuning(1) 0x7 UHS-I DR50 4-bit PHY operating 1.8 V, 50 MHz 0x1 0x9 0x1 Tuning(1) 0x7 UHS-I SDR104 4-bit PHY operating 1.8, V 200 MHz 0x1 0x6 0x1 Tuning(1) 0x7 (1) Tuning means this mode requires a tuning algorithm to be used for optimal input timing Table 7-76 presents timing conditions for MMC1. www.ti.com AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 201 Product Folder Links: AM2434 AM2432 AM2431 |
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