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AM2434...ALV 数据表(PDF) 205 Page - Texas Instruments |
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AM2434...ALV 数据表(HTML) 205 Page - Texas Instruments |
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205 / 280 page  7.10.5.12.2.3 UHS–I SDR12 Mode Table 7-81, Figure 7-69, Table 7-82, and Figure 7-70 present timing requirements and switching characteristics for MMC1 – UHS-I SDR12 Mode. Table 7-81. Timing Requirements for MMC1 – UHS-I SDR12 Mode see Figure 7-69 NO. MIN MAX UNIT SDR121 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising edge 21.65 ns SDR122 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising edge 1.67 ns SDR123 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge 21.65 ns SDR124 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge 1.67 ns MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x SDR121 SDR122 SDR123 SDR124 MMC[ ]_CLK x Figure 7-69. MMC1 – UHS-I SDR12 – Receive Mode Table 7-82. Switching Characteristics for MMC1 – UHS-I SDR12 Mode see Figure 7-70 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 25 MHz SDR125 tc(clk) Cycle time, MMC1_CLK 40 ns SDR126 tw(clkH) Pulse duration, MMC1_CLK high 18.7 ns SDR127 tw(clkL) Pulse duration, MMC1_CLK low 18.7 ns SDR128 td(clkL-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition -13.6 13.6 ns SDR129 td(clkL-dV) Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition -13.6 13.6 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x SDR125 SDR127 SDR126 SDR128 SDR129 SDR128 SDR129 Figure 7-70. MMC1 – UHS-I SDR12 – Transmit Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 205 Product Folder Links: AM2434 AM2432 AM2431 |
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