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AM2434...ALV 数据表(PDF) 208 Page - Texas Instruments |
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AM2434...ALV 数据表(HTML) 208 Page - Texas Instruments |
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208 / 280 page  7.10.5.12.2.6 UHS–I DDR50 Mode Table 7-86, Figure 7-74, Table 7-87, and Figure 7-75 present timing requirements and switching characteristics for MMC1 – UHS-I DDR50 Mode. Table 7-86. Timing Requirements for MMC1 – UHS-I DDR50 Mode see Figure 7-74 NO. MIN MAX UNIT DDR501 tsu(cmdV-clk) Setup time, MMC1_CMD valid before MMC1_CLK rising edge 2.99 ns DDR502 th(clk-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising edge 1.91 ns DDR503 tsu(dV-clk) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK transition -0.06 ns DDR504 th(clk-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK transition 1.91 ns MMC[x] CLK _ MMC[x] CMD _ MMC[x] DAT3 _ [ :0] DDR501 DDR502 DDR504 DDR503 DDR503 DDR504 Figure 7-74. MMC1 – UHS-I DDR50 – Receive Mode Table 7-87. Switching Characteristics for MMC1 – UHS-I DDR50 Mode see Figure 7-75 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 50 MHz DDR505 tc(clk) Cycle time, MMC1_CLK 20 ns DDR506 tw(clkH) Pulse duration, MMC1_CLK high 9.2 ns DDR507 tw(clkL) Pulse duration, MMC1_CLK low 9.2 ns DDR508 td(clk-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition 1.2 13.1 ns DDR509 td(clk-dV) Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition 1.2 6.35 ns MMC[x] CLK _ MMC[x] CMD _ MMC[x] DAT3 _ [ :0] DDR508 DDR509 DDR509 DDR505 DDR506 DDR507 Figure 7-75. MMC1 – UHS-I DDR50 – Transmit Mode AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 www.ti.com 208 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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