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AM2434...ALV 数据表(PDF) 206 Page - Texas Instruments |
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AM2434...ALV 数据表(HTML) 206 Page - Texas Instruments |
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206 / 280 page  7.10.5.12.2.4 UHS–I SDR25 Mode Table 7-83, Figure 7-71, Table 7-84, and Figure 7-72 present timing requirements and switching characteristics for MMC1 – UHS-I SDR25 Mode. Table 7-83. Timing Requirements for MMC1 – UHS-I SDR25 Mode see Figure 7-71 NO. MIN MAX UNIT SDR251 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising edge 2.15 ns SDR252 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising edge 1.67 ns SDR253 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge 2.15 ns SDR254 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge 1.67 ns MMC[ ]_CLK x MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x SDR251 SDR252 SDR253 SDR254 Figure 7-71. MMC1 – UHS-I SDR25 – Receive Mode Table 7-84. Switching Characteristics for MMC1 – UHS-I SDR25 Mode see Figure 7-72 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 50 MHz SDR255 tc(clk) Cycle time, MMC1_CLK 20 ns SDR256 tw(clkH) Pulse duration, MMC1_CLK high 9.2 ns SDR257 tw(clkL) Pulse duration, MMC1_CLK low 9.2 ns SDR258 td(clkL-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition -7.1 3.1 ns SDR259 td(clkL-dV) Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition -7.1 3.1 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ _ [3:0] x] SDR255 SDR257 SDR256 SDR258 SDR259 SDR258 SDR259 Figure 7-72. MMC1 – UHS-I SDR25 – Transmit Mode AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 www.ti.com 206 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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