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STM32F405 数据表(PDF) 150 Page - STMicroelectronics |
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STM32F405 数据表(HTML) 150 Page - STMicroelectronics |
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150 / 204 page  Electrical characteristics STM32F405xx, STM32F407xx 150/203 DS8626 Rev 9 Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0 - ns tsu(NWAIT- CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization. Table 80. Synchronous multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter Min Max Unit FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) th(CLKH-DV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894f FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) |
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