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STM32F405 数据表(PDF) 149 Page - STMicroelectronics

部件名 STM32F405
功能描述  Arm® Cortex®-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  204 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F405 数据表(HTML) 149 Page - STMicroelectronics

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DS8626 Rev 9
149/203
STM32F405xx, STM32F407xx
Electrical characteristics
Figure 59. Synchronous multiplexed PSRAM write timings
Table 80. Synchronous multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
2THCLK
-ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)
-
1
ns
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)
1
-
ns
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
-
0
ns
td(CLKL-
NADVH)
FSMC_CLK low to FSMC_NADV high
0
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
8
-
ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
-
0.5
ns
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high
0
-
ns
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid
0
-
ns
td(CLKL-DATA)
FSMC_A/D[15:0] valid data after FSMC_CLK
low
-3
ns
FSMC_CLK
FSMC_NEx
FSMC_NADV
FSMC_A[25:16]
FSMC_NWE
FSMC_AD[15:0]
AD[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKL-AIV)
td(CLKL-NWEH)
td(CLKL-NWEL)
td(CLKL-NBLH)
td(CLKL-ADV)
td(CLKL-ADIV)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14992g
td(CLKL-Data)
FSMC_NBL



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