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STM32F405 数据表(PDF) 145 Page - STMicroelectronics

部件名 STM32F405
功能描述  Arm® Cortex®-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  204 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F405 数据表(HTML) 145 Page - STMicroelectronics

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DS8626 Rev 9
145/203
STM32F405xx, STM32F407xx
Electrical characteristics
Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms
NBL
Data
FSMC_NBL[1:0]
FSMC_AD[15:0]
tv(BL_NE)
th(Data_NE)
Address
FSMC_A[25:16]
tv(A_NE)
FSMC_NWE
t v(A_NE)
ai14892b
Address
FSMC_NADV
t v(NADV_NE)
tw(NADV)
tsu(Data_NE)
th(AD_NADV)
FSMC_NE
FSMC_NOE
tw(NE)
t w(NOE)
tv(NOE_NE)
t h(NE_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE)
th(Data_NOE)
Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
3THCLK–1
3THCLK+1
ns
tv(NOE_NE) FSMC_NEx low to FSMC_NOE low
2THCLK–0.5
2THCLK+0.5
ns
tw(NOE)
FSMC_NOE low time
THCLK–1
THCLK+1
ns
th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time
0
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
3
ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
1
2
ns
tw(NADV)
FSMC_NADV low time
THCLK– 2
THCLK+1
ns
th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high)
THCLK
-ns
th(A_NOE)
Address hold time after FSMC_NOE high
THCLK–1
-
ns
th(BL_NOE)
FSMC_BL time after FSMC_NOE high
0
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
2
ns
tsu(Data_NE) Data to FSMC_NEx high setup time
THCLK+4
-
ns
tsu(Data_NOE) Data to FSMC_NOE high setup time
THCLK+4
-
ns
th(Data_NE) Data hold time after FSMC_NEx high
0
-
ns
th(Data_NOE) Data hold time after FSMC_NOE high
0
-
ns
1. CL = 30 pF.
2. Guaranteed by characterization.



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