STM32F405 datasheet(141/204 Pages) STMICROELECTRONICS

141 / 204 page

DS8626 Rev 9

141/203

STM32F405xx, STM32F407xx

Electrical characteristics

Offset(4)

Offset error

(difference between

measured value at Code

(0x800) and the ideal value

= VREF+/2)

±10

Given for the DAC in 12-bit

configuration

±3

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

±12

LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

Gain

error(4)

Gain error

±0.5

Given for the DAC in 12-bit

configuration

tSETTLING(4)

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±4LSB

-3

µs

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

THD(4)

Total Harmonic Distortion

Buffer ON

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

Update

rate(2)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

MS/s

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

tWAKEUP(4)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

µs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

input code between lowest and

highest possible ones.

PSRR+ (2)

Power supply rejection ratio

(to VDDA) (static DC

measurement)

–67

–40

No RLOAD, CLOAD = 50 pF

1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of

an external power supply supervisor (refer to Section : Internal reset OFF).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

4. Guaranteed by characterization.

Table 74. DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

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