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STM32F405 数据表(PDF) 144 Page - STMicroelectronics

部件名 STM32F405
功能描述  Arm® Cortex®-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  204 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F405 数据表(HTML) 144 Page - STMicroelectronics

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Electrical characteristics
STM32F405xx, STM32F407xx
144/203
DS8626 Rev 9
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
3THCLK
3THCLK+ 4
ns
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
THCLK–0.5
THCLK+0.5
ns
tw(NWE)
FSMC_NWE low time
THCLK–1
THCLK+2
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
THCLK–1
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
0
ns
th(A_NWE)
Address hold time after FSMC_NWE high
THCLK– 2
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
1.5
ns
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
THCLK– 1
-
ns
tv(Data_NE)
Data to FSMC_NEx low to Data valid
-
THCLK+3
ns
th(Data_NWE)
Data hold time after FSMC_NWE high
THCLK–1
-
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
2
ns
tw(NADV)
FSMC_NADV low time
-
THCLK+0.5
ns
NBL
Data
FSMC_NEx
FSMC_NBL[1:0]
FSMC_D[15:0]
tv(BL_NE)
th(Data_NWE)
FSMC_NOE
Address
FSMC_A[25:0]
tv(A_NE)
tw(NWE)
FSMC_NWE
tv(NWE_NE)
t h(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(Data_NE)
tw(NE)
ai14990
FSMC_NADV(1)
t v(NADV_NE)
tw(NADV)



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