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STM32F405 数据表(PDF) 193 Page - STMicroelectronics |
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STM32F405 数据表(HTML) 193 Page - STMicroelectronics |
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193 / 204 page ![]() DS8626 Rev 9 193/203 STM32F405xx, STM32F407xx Revision history 24-Jan-2012 2 (continued) Updated Table 61: USB HS clock timing parameters Updated Table 67: ADC characteristics. Updated Table 68: ADC accuracy at fADC = 30 MHz. Updated Note 1 in Table 74: DAC characteristics. Section 5.3.26: FSMC characteristics: updated Table 75 toTable 86, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 59: Synchronous multiplexed PSRAM write timings. Updated Table 98: Package thermal characteristics. Appendix A.1: USB OTG full speed (FS) interface solutions: modified Figure 93: USB controller configured as peripheral-only and used in Full speed mode added Note 2, updated Figure 94: USB controller configured as host-only and used in full speed mode and added Note 2, changed Figure 95: USB controller configured in dual mode and used in full speed mode and added Note 3. Appendix A.2: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, and updated Figure 96: USB controller configured as peripheral, host, or dual-mode and used in high speed mode and added Note 2. Added Appendix A.3: Ethernet interface solutions. Table 99. Document revision history (continued) Date Revision Changes |
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