L99LD21 datasheet(26/73 Pages) STMICROELECTRONICS

26 / 73 page

Functional description

L99LD21

26/73

DS11130 Rev 5

The PWM dimming could be achieved in two different ways:

•

Through direct input, DIN

•

With integrated PWM generator

Dimming with direct input

The signal applies to buck1, buck2 or both, depending on DIN mapping bit configuration

(see bits <15:14> and bits <13:12> on Table 16: CR#3: Control Register 3). If the control

registers are configured accordingly, one (or both) buck converter(s) are activated and

directly controlled by DIN pin.

The default configuration is set in order to allow direct driving only for buck1, whilst buck2 is

turned off. In case of limp home function, the default conditions are applied.

PWM control through DIN has to take into account the DIN filter time (tDIN_FT, 32 µs typical)

on rising edge to properly set the desired duty cycle.

Dimming with integrated PWM generator

This function allows modifying the average current on the LEDs by means of a dedicated

control register (see bits <23:14> and bits <13:4> on Table 14: CR#1: Control Register 1).

This function must be activated setting the right mapping bits configuration inside the control

To set duty cycle, a 10-bit number must be written in the corresponding register, resulting in

a 1024 steps of resolution. The duty cycle is determined through the following equation:

Where N is the 10-bit number.

The PWM frequency is depending on the PWM_CLK input signal with the following

equation:

Where PWM_LF is the LEDs dimming frequency.

If PWM signal fails, an error bit is reported in the STATUS register where PWMCLK fail is

located. An internal fallback oscillator is enabled in order to provide a fixed PWM frequency

clock signal (FFALLBACK_CLK), whilst no changes is applied on the duty cycle.

Once the external PWM is available again and after a read & clear operation on Status

clock (see Figure 14).

4.3

Protections

4.3.1

Temperature warning

The device integrates a temperature warning with two thresholds TW1 and TW2 in each

buck’s mosfet. If the Tj of the buck mosfet1 or buck mosfet2 rises above TW1 or TW2, the

status bit TWxy is set (x = 1 or x = 2, it stands for the buck1 or buck2, y = 1 or y = 2, it

stands for the TW1 or TW2) . TWXY bit is set on the status registers: SR#1<4:3> for Buck1

1024

------------- 100

⋅

PWM_LF

PWM_CLK

1024

-----------------------------

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