L99LD21 datasheet(35/73 Pages) STMICROELECTRONICS

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DS11130 Rev 5

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L99LD21

SPI functional description

CR#3: Control Register 3

Address:

0x03h

Type:

R/W

Active mode Enable Bit:

0: Device stays in Limp Home (if GOSTBY = 0). This status is assumed

immediately after a wake up (CSN low or DIN High for a time >

tWAKE_UP)

1: Device Enabled for Active mode operation (if GOSTBY = 0).

EN can be set to 1 only if UNLOCK = 1; in other words, trying to set this

bit to 1 when UNLOCK = 0 will have no effects and it will maintain its

previous value.

EN can be reset to 0 also when UNLOCK = 0.

To set Active mode it is necessary to send two consecutive SPI frames

as follows:

1st SPI write operation to set UNLOCK bit to 1 (CR#1, bit1)

2nd SPI write operation to set GOSTBY bit to 0 and EN bit to 1

Set by OTP

(DEF_MS)

Master/Slave bit

0: Device is Master (pin SYNC_IO is an output, providing a 180° phase

shifted replica of internal Boost clock)

1: Device is Slave (pin SYNC_IO is an input and it is used as a clock for

the Boost)

Parity bit

ODD parity bit check

Table 15. CR#2: Control Register 2 (continued)

Bit

Default

Name

Description

9876

543210

PH1

PH2

BST_FREQ

B_IN_W1

B_IN_W2

Table 16. CR#3: Control Register 3

Bit

Default

Name

Description

23÷20

0000

PH1

4 bit phase selection for Buck1:

Phase shift = PH1 * 360 / 16

19÷16

0000

PH2

4 bit phase selection for Buck2:

Phase shift = PH1 * 360 / 16

15÷14

DIN_MAP1

Buck1 DIN map (see Table 19)

13÷12

DIN_MAP2

Buck2 DIN map (see Table 19)

11÷10

BST_REF

Boost Reference Voltage(1)

11: VFB_REF[11]

10: VFB_REF[10]

01: VFB_REF[01]

00: VFB_REF[00]

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