L99LD21 datasheet(36/73 Pages) STMICROELECTRONICS

36 / 73 page

SPI functional description

L99LD21

36/73

DS11130 Rev 5

CR#4: Control Register 4

Address:

0x04h

Type:

R/W

9÷7

011

BST_FREQ

Boost Frequency Clock selection bits (see Table 20)

PWM_SYNC

PWMSYNC:

0: PWM Counter not reset;

1: PWM Counter Reset (note that this bit is automatically reset after

counter reset)

5÷4

B_IN_W1

Buck Input Voltage Window for Buck1 (see Table 21)

3÷2

B_IN_W2

Buck Input Voltage Window for Buck2 (see Table 21)

Set by OTP

(DEF_BSTDIS)

BST_DIS

BST_DIS can be set to 1 only if UNLOCK = 1; in other words, if the µC

tries to set this bit to 1 when UNLOCK = 0 it maintains its previous

value.

BST_DIS can be reset to 0 also when UNLOCK = 0

0: Boost enabled

1: Boost disabled:

For disabling the boost It is necessary to send two distinct SPI frame

as follows:

1st SPI Register write: set UNLOCK bit to 1

2nd SPI Register write: set BST_DIS to 1

Parity bit

ODD parity bit check

See Table 2.

Table 16. CR#3: Control Register 3 (continued)

Bit

Default

Name

Description

9876

543210

Reserved

Unused

Table 17. CR#4: Control Register 4

Bit

Default

Name

Description

WD_TRIG

In order to keep device in Active mode, this bit must be cyclically

toggled within a period equal to tWD to refresh the watchdog.

22÷21

Reserved

Note: when writing on this register, bit 21 and 22 must be set to 00

20÷1

Unused

Parity bit

ODD parity bit check

L99LD21 数据表(PDF) 36 Page - STMicroelectronics

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