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L99LD21 数据表(PDF) 32 Page - STMicroelectronics |
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L99LD21 数据表(HTML) 32 Page - STMicroelectronics |
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32 / 73 page ![]() SPI functional description L99LD21 32/73 DS11130 Rev 5 3Eh Customer Trimming Register R/W (W only when EOT bit = 0) CT: Customer Trimming Register 3Fh Advanced Operation Code Clear A R&C operation to this address causes all status registers to be cleared Table 13. ROM memory map Address Name Access Content Comments 00h Company Code R 00h STMicroelectronics 01h Device family R 02h LED product family 02h Device number 1 R 55h ‘U’ in ASCII 03h Device number 2 R 41h ‘A’ in ASCII 04h Device number 3 R 52h ‘R’ in ASCII 05h Device number 4 R 07h ‘7’ in hex 0Ah Silicon version R 04h Fifth version 10h SPI Mode R 31h Bit7 = 0, burst read is disabled SPI data length = 32 bits Bit6, DL2 = 0 Bit5, DL1 = 1 Bit4, DL0 = 1 Bit3, SPI8 = 0: 8 bit frame option not available Bit2 =0 Parity check is used Bit1, S1=0 Bit0, S0=1 11h WD Type 1 R 4Ah A WD is implemented Bit7, WD1 =0 Bit6, WD0 =1 WD period 50 ms = 10 * 5 ms -> WT[5:0] = 0xA Bit5, WT5 = 0 Bit4, WT4 = 0 Bit3, WT3 = 1 Bit2, WT2 = 0 Bit1, WT1 = 1 Bit0, WT0 = 0 13h WD bit pos. 1 R 44h Bit7, WB1 = 0 Bit6, WB2 = 1 WBA[5-0], Bit[5-0] = address of the configuration register, where the WD bit is located = 04d = 000100b Table 12. RAM memory map (continued) Address Name Access Content |
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