L99LD21 datasheet(31/73 Pages) STMICROELECTRONICS

31 / 73 page

DS11130 Rev 5

31/73

L99LD21

SPI functional description

5.3

Address mapping

Table 11. Global Status Byte description

Bit

Name

Description

GSBN

Global Status Bit Not

This bit is a NOR combination of the remaining bits of this register:

RSTB nor SPIE nor FE2 nor FE1 nor DE nor GW nor FS

RSTB

Reset Bit

The RSTB indicates a device reset. In case this bit is set, all internal Control

Registers are set to default and kept in that state until the bit is automatically

cleared by any valid SPI communication.

SPIE

SPI Error

The SPIE is a logical OR combination of errors related to a wrong SPI

communication (SDI stuck, wrong number of clock, parity check error)

FE2

Functional Error 2 (logic OR combination of errors which does not cause parts

of the device to be disabled)

TOFF1_MAX or TOFF2_MAX or TOFF1_MIN or TOFF2_MIN or

TON_MAX_OP1 or TON_MAX_OP2

FE1

Functional Error 1 (logic OR combination of critical errors which cause parts of

the device to be disabled)

VS_UV or OL1 or OL2 or OVT1 or OVT2 or SHT1 or SHT2 ot TON_MIN_OP1

or TON_MIN_OP2 or BST_FB_FAIL

Device error

PWMCLK_FAIL or N_PWR_GOOD or BST_OVP

Global warning

TW11 or TW12 or TW21 or TW22

Fail safe

If this bit is set, the device is in limp home mode

Table 12. RAM memory map

Address

Name

Access

Content

01h

Control Register 1

R/W

CR#1: 1st Control Register

02h

Control Register 2

R/W

CR#2: 2nd Control Register

03h

Control Register 3

R/W

CR#3: 3rd Control Register

04h

Control Register 4

R/W

CR#4: 4th Control Register

05h

Status Register 1

R/C

SR#1: 1st Status Register

06h

Status Register 2

R/C

SR#2: 2nd Status Register

07h

Status Register 3

R/C

SR#3: 3rd Status Register

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