L99LD21 datasheet(27/73 Pages) STMICROELECTRONICS

27 / 73 page

DS11130 Rev 5

27/73

L99LD21

Functional description

and SR#2<22:21> for Buck2. Thermal warning is also reported in the Global Status Byte

If the Tj drops below the temperature warning reset threshold 1 (TW1-TW1_HYS),

respectively TW2 – TW2_HYS, the corresponding status bit is automatically reset.

As long as the Tj does not exceed the over temperature shutdown, the device does not

latches off the buck mosfets, even if a temperature warning is detected.

4.3.2

Overtemperature shutdown

If the junction temperature of one of the buck mosfets rises above the shutdown

temperature TTSD, an overtemperature event (OVT) is detected. The channel is switched off

and the corresponding bit (OVT1 or OVT2) is set in the status register SR#1<5> for Buck1

and SR#2<23> for Buck2.

Overtemperature events are also reported in the Global Status Byte register and in

particular bit 27 FE1 is set.

In normal mode the corresponding buck converter is latched off, until the following

conditions are fulfilled:

TJX drops below the thermal shutdown reset threshold TTSD-TTSD_HYS.

Subsequently the microcontroller sends a read and clear command, in order to reset

OVT1 or OVT2 bit located in the Status register SR#1<5> or SR#2<23>.

In fail safe mode (Limp Home), the device applies an auto restart of the fault buck converter

with a period equal to tAUTORESTART, provided that the TJX falls below TSD reset threshold

(TTSD-TTSD_HYS).

4.3.3

VS under voltage lockout

If the VS supply falls below VS_UV (VS under voltage threshold), the boost controller and the

buck converters will be deactivated, regardless of the SPI control registers or DIN.

This feature is implemented, in order to avoid an operation of the external mosfet of the

boost controller in linear mode, due to a too low gate driver supply.

4.3.4

Buck TON minimum operation

Buck minimum on time operation is detected when the corresponding failure counter counts

N_Ton_min_fail switching cycles (also nonconsecutive), during which ILx_PEAK is reached

between TBLANK_BUCK and TON_MIN_BUCK. In normal mode (Active mode), once minimum

TON operation is validated, flag TON_MIN_OPx is set and the corresponding Buckx converter

is latched off, until the microcontroller sends a frame and clears the corresponding status bit

(SR#1<2> and SR#1<1>).

In fail safe mode (Limp Home), once a minimum TON violation is validated, the

corresponding buck converter is latched off until automatically cleared by an auto-restart

procedure, with a period equal to tAUTORESTART.

The failure counter is not incremented during the startup phase (TSTARTUP). The failure

counter is reset if Nton_min_fail_reset consecutive pulses are detected with TON longer

than TON_MIN_BUCK.

L99LD21 数据表(PDF) 27 Page - STMicroelectronics

L99LD21 数据表(HTML) 27 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载