| 数据搜索系统,热门电子元器件搜索 |
|
STM32H757AI 数据表(PDF) 149 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32H757AI 数据表(HTML) 149 Page - STMicroelectronics |
|
149 / 251 page ![]() DS12931 Rev 1 149/251 STM32H757xI Electrical characteristics 230 Figure 25. MIPI D-PHY HS/LP clock lane transition timing diagram Figure 26. MIPI D-PHY HS/LP data lane transition timing diagram 6.3.13 MIPI D-PHY regulator characteristics The parameters given in Table 63 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. MS38282V1 Clock Lane Data Lane TLPX THS-PREPARE TCLK-PRE TCLK-ZERO TCLK-PREPARE TLPX THS-EXIT TCLK-TRAIL TCLK-POST VIL VIL TEOT MS38283V1 Clock Lane THS-PREPARE TLPX THS-TRAIL THS-EXIT LP-01 LP-00 LP-11 Data Lane VIL TREOT TEOT THS-ZERO Table 63. DSI regulator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDDSI Regulator output voltage on VDDDSI -1.62 - - V VDD12DSI 1.2 V internal voltage on VDD12DSI - 1.15 1.20 1.26 CEXT External capacitor on VCAPDSI -0.5 2.2(2) 3.3 μF ESR External serial resistor - 0 25 600 mΩ ILOAD Static load current - - - 50 mA IDDDSIREG Regulator power consumption on VDDDSI ILOAD = 0 mA 110 170 220 µA ILOAD = 50 mA 140 200 260 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |