KSZ9567RTXI-TR datasheet(226/232 Pages) MICROCHIP

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KSZ9567R

DS00002329D-page 226

 2017-2019 Microchip Technology Inc.

APPENDIX A: DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Revision

Section/Figure/Entry

Correction

DS00002329D (07-08-19)

Table 4-14, "Transmit Tail

Tag Format (from Host to

Switch)"

Bit 7 changed to “15:11” and description changed

to “Reserved”.

Section 2.1, "General

Description," on page 8

Updated first bullet to indicate the non-blocking

wire-speed Ethernet switch fabric supports 1 Gbps

on RGMII.

Section 4.1.5, "Pair-Swap,

Alignment, and Polarity

Check"

Updated first bullet description.

Section 4.3.3, "Back-Off

Algorithm"

Updated second sentence.

Section 4.3.5, "Legal Packet

Size"

Simplified paragraph for clarity.

Section 4.3.6, "Flow Control"

Simplified last sentence of third paragraph.

Table 4-10

Updated Action description for the Yes entry.

Section 4.4.3.2.1, Tag Inser-

tion and Removal

Updated last paragraph of section.

Section 4.4.8, "Multiple

Spanning Tree Support"

Updated second sentence.

Table 4-17, "ACL Matching

Rule Parameters for MD =

01"

Corrected ENB[1:0] “01” and “10” definitions to

match those in Table 4-16, "Matching Rule

Options".

Section 4.5, "IEEE 1588

Precision Time Protocol"

Added additional paragraph to end of section.

Section 4.12, "In-Band Man-

agement"

• Added to last sentence of first paragraph.

• Added additional sentence to end of second

paragraph.

• Added additional sentence to end of sixth

paragraph.

Section 5.1.6.17, "Time-

stamp Control and Status

Updated bit 6 definition.

Section 5.2.1.7, "Port Oper-

ation Control 0 Register"

Updated bit 6 and 7 descriptions to include refer-

ences to the MAC and additional clarification.

Section 5.2.2.15, "PHY

Remote Loopback Register"

Simplified bit 8 description.

Section 5.2.4.1, "Port MAC

Control 0 Register," on

page 156

Bit 0 made reserved.

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