KSZ9567RTXI-TR datasheet(170/232 Pages) MICROCHIP

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KSZ9567R

DS00002329D-page 170

 2017-2019 Microchip Technology Inc.

5.2.7.3

Port Ingress MAC Control Register

VLAN Priority Classification

1 = Enable VLAN priority classification for ingress packets on port

0 = Disabled VLAN classification

R/W

802.1p Priority Classification

1 = Enable 802.1p priority classification for ingress packets on port

0 = Disable 802.1p priority classification

R/W

Diffserv Priority Classification

1 = Enable Diffserv priority classification for ingress packets on port

0 = Disable Diffserv priority classification

R/W

ACL Priority Classification

1 = Enable ACL priority classification for ingress packets on port

0 = Disable ACL priority classification

R/W

Address:

0xN802

Port N: 1-7

Size:

8 bits

Bits

Description

Type

Default

User Priority Ceiling

1 = If a packet’s “user priority field” is greater than the “user priority field” in

the port default tag register, replace the packet’s user priority field with the

user priority field in the port default tag from the Port Default Tag 0 Register.

0 = Do not replace the user priority field at this port.

R/W

6:5

RESERVED

Discard Untagged Packets

This bit should be left as 0 for the host port.

1 = Any ingress packet at this port without an IEEE 802.1Q tag is discarded.

0 = Do not discard.

R/W

Discard Tagged Packets

1 = Any ingress packet at this port with an IEEE 802.1Q tag is discarded.

0 = Do not discard.

R/W

2:0

Port Default Priority Classification

If Diffserv classification, 802.1p classification and VLAN classification are not

enabled or fail to classify, ingress packets at this port will be classified with

the priority specified here. Possible values are 0 to 7.

R/W

000b

Bits

Description

Type

Default

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