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M58WR032EB 数据表(PDF) 61 Page - STMicroelectronics |
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M58WR032EB 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 81 page  61/81 M58WR032ET, M58WR032EB Table 38. Bank and Erase Block Region 1 Information M58WR032ET (top) M58WR032EB (bottom) Description Offset Data Offset Data (P+19)h =52h 07h (P+19)h =52h 01h Number of identical banks within Bank Region 1 (P+1A)h =53h 00h (P+1A)h =53h 00h (P+1B)h =54h 11h (P+1B)h =54h 11h Number of program or erase operations allowed in region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1C)h =55h 00h (P+1C)h =55h 00h Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1D)h =56h 00h (P+1D)h =56h 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1E)h =57h 01h (P+1E)h =57h 02h Types of erase block regions in region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) (P+1F)h =58h 07h (P+1F)h =58h 07h Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+20)h =59h 00h (P+20)h =59h 00h (P+21)h =5Ah 00h (P+21)h =5Ah 20h (P+22)h =5Bh 01h (P+22)h =5Bh 00h (P+23)h =5Ch 64h (P+23)h =5Ch 64h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles × 1000 (P+24)h =5Dh 00h (P+24)h =5Dh 00h (P+25)h =5Eh 01h (P+25)h =5Eh 01h Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 5Eh 01 5Eh 01 (P+26)h =5Fh 03h (P+26)h =5Fh 03h Bank Region 1 (Erase Block Type 1): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+27)h =60h 06h Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+28)h =61h 00h (P+29)h =62h 00h (P+2A)h =63h 01h (P+2B)h =64h 64h Bank Region 1 (Erase Block Type 2) Minimum block erase cycles × 1000 (P+2C)h =65h 00h (P+2D)h =66h 01h Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved |
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