M58WR032EB datasheet(62/81 Pages) STMICROELECTRONICS

62 / 81 page

M58WR032ET, M58WR032EB

62/81

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks

that are made up of the parameter and main blocks.

Table 39. Bank and Erase Block Region 2 Information

(P+2E)h =67h

03h

Bank Region 1 (Erase Block Type 2): Page mode and

synchronous mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

M58WR032ET (top)

M58WR032EB (bottom)

Description

Offset

Data

Offset

Data

(P+27)h =60h

01h

(P+2F)h =68h

07h

Number of identical banks within bank region 2

(P+28)h =61h

00h

(P+30)h =69h

00h

(P+29)h =62h

11h

(P+31)h =6Ah

11h

Number of program or erase operations allowed in bank region

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+2A)h =63h

00h

(P+32)h =6Bh

00h

Number of program or erase operations allowed in other banks

while a bank in this region is programming

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+2B)h =64h

00h

(P+33)h =6Ch

00h

Number of program or erase operations allowed in other banks

while a bank in this region is erasing

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+2C)h =65h

02h

(P+34)h =6Dh

01h

Types of erase block regions in region 2

n = number of erase block regions with contiguous same-size

erase blocks.

Symmetrically blocked banks have one blocking region.(2)

(P+2D)h =66h

06h

(P+35)h =6Eh

07h

Bank Region 2 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

(P+2E)h =67h

00h

(P+36)h =6Fh

00h

(P+2F)h =68h

00h

(P+37)h =70h

00h

(P+30)h =69h

01h

(P+38)h =71h

01h

(P+31)h =6Ah

64h

(P+39)h =72h

64h

Bank Region 2 (Erase Block Type 1)

Minimum block erase cycles × 1000

(P+32)h =6Bh

00h

(P+3A)h =73h

00h

(P+33)h =6Ch

01h

(P+3B)h =74h

01h

Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

(P+34)h =6Dh

03h

(P+3C)h =75h

03h

Bank Region 2 (Erase Block Type 1): Page mode and

synchronous mode capabilities (defined in Table 36.)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

M58WR032ET (top)

M58WR032EB (bottom)

Description

Offset

Data

Offset

Data

M58WR032EB 数据表(PDF) 62 Page - STMicroelectronics

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