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M58WR032EB 数据表(PDF) 25 Page - STMicroelectronics |
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M58WR032EB 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 81 page ![]() 25/81 M58WR032ET, M58WR032EB Table 8. Status Register Bits Note: Logic level ’1’ is High, ’0’ is Low. Bit Name Type Logic Level Definition SR7 P/E.C. Status Status ’1’ Ready ’0’ Busy SR6 Erase Suspend Status Status ’1’ Erase Suspended ’0’ Erase In progress or Completed SR5 Erase Status Error ’1’ Erase Error ’0’ Erase Success SR4 Program Status Error ’1’ Program Error ’0’ Program Success SR3 VPP Status Error ’1’ VPP Invalid, Abort ’0’ VPP OK SR2 Program Suspend Status Status ’1’ Program Suspended ’0’ Program In Progress or Completed SR1 Block Protection Status Error ’1’ Program/Erase on protected Block, Abort ’0’ No operation to protected blocks SR0 Bank Write Status Status ’0’ SR7 = ‘0’ Program or erase operation in addressed bank SR7 = ‘1’ No Program or erase operation in the device '1' SR7 = ‘0’ Program or erase operation in a bank other than the addressed bank SR7 = ‘1’ Not Allowed Multiple Word Program Status (Enhanced Factory Program mode) Status '1' SR7 = ‘0’ the device is NOT ready for the next word SR7 = ‘1’ Not Allowed '0' SR7 = ‘0’ the device is ready for the next Word SR7 = ‘1’ the device is exiting from EFP |
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