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DSP56321RM/D 数据表(PDF) 29 Page - NXP Semiconductors |
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DSP56321RM/D 数据表(HTML) 29 Page - NXP Semiconductors |
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29 / 88 page ![]() 2-5 AC Electrical Characteristics Note: If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by setting XTLD (PCTL Register bit 2 = 1—see the DSP56321T Reference Manual). The external square wave source connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the EXTAL input and the internal clock signals. Table 2-5. External Clock Operation No. Characteristics Symbol 220 MHz 240 MHz Min Max Min Max 1 Frequency of EXTAL (EXTAL Pin Frequency)1 • With DPLL disabled • With DPLL enabled2 Ef DEFR = PDF × PDFR 0 MHz 16 MHz 220 MHz 220 MHz 0 MHz 16 MHz 240 MHz 240 MHz 2 EXTAL input high3 • With DPLL disabled (46.7%–53.3% duty cycle4) • With DPLL enabled (42.5%–57.5% duty cycle4) ETH 2.13 ns 1.93 ns ∞ 35.9 ns 1.95 ns 1.77 ns ∞ 35.9 ns 3 EXTAL input low4 • With DPLL disabled (46.7%–53.3% duty cycle4) • With DPLL enabled (42.5%–57.5% duty cycle4) ETL 2.13 ns 1.93 ns ∞ 35.9 ns 1.95 ns 1.77 ns ∞ 35.9 ns 4 EXTAL cycle time3 • With DPLL disabled • With DPLL enabled ETC 4.55 ns 4.55 ns ∞ 62.5 ns 4.17 ns 4.17 ns ∞ 62.5 ns 7 Instruction cycle time = ICYC = ETC • With DPLL disabled • With DPLL enabled ICYC 9.1 ns 4.55 ns ∞ 1.6 µs 8.34 ns 4.17 ns ∞ 1.6 µs Notes: 1. The rise and fall time of this external clock should be 2 ns maximum. 2. Refer to Table 2-6 for a description of PDF and PDFR. 3. Measured at 50 percent of the input transition. 4. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. Figure 2-2. External Input Clock Timing EXTAL VILX VIHX Midpoint Note: The midpoint is 0.5 (VIHX + VILX). ETH ETL ETC 3 4 2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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