数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

DSP56321RM/D 数据表(PDF) 29 Page - NXP Semiconductors

部件名 DSP56321RM/D
功能描述  24-Bit Digital Signal Processor
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

DSP56321RM/D 数据表(HTML) 29 Page - NXP Semiconductors

Back Button DSP56321RM/D Datasheet HTML 25Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 26Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 27Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 28Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 29Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 30Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 31Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 32Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 33Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 88 page
background image
2-5
AC Electrical Characteristics
Note:
If an externally-supplied square wave voltage source is used, disable the internal oscillator
circuit during bootup by setting XTLD (PCTL Register bit 2 = 1—see the DSP56321T
Reference Manual). The external square wave source connects to EXTAL; XTAL is not
physically connected to the board or socket. Figure 2-2 shows the EXTAL input and the internal
clock signals.
Table 2-5. External Clock Operation
No.
Characteristics
Symbol
220 MHz
240 MHz
Min
Max
Min
Max
1
Frequency of EXTAL (EXTAL Pin Frequency)1
With DPLL disabled
With DPLL enabled2
Ef
DEFR = PDF
× PDFR
0 MHz
16 MHz
220 MHz
220 MHz
0 MHz
16 MHz
240 MHz
240 MHz
2
EXTAL input high3
With DPLL disabled (46.7%–53.3% duty cycle4)
With DPLL enabled (42.5%–57.5% duty cycle4)
ETH
2.13 ns
1.93 ns
35.9 ns
1.95 ns
1.77 ns
35.9 ns
3
EXTAL input low4
With DPLL disabled (46.7%–53.3% duty cycle4)
With DPLL enabled (42.5%–57.5% duty cycle4)
ETL
2.13 ns
1.93 ns
35.9 ns
1.95 ns
1.77 ns
35.9 ns
4
EXTAL cycle time3
With DPLL disabled
With DPLL enabled
ETC
4.55 ns
4.55 ns
62.5 ns
4.17 ns
4.17 ns
62.5 ns
7
Instruction cycle time = ICYC = ETC
With DPLL disabled
With DPLL enabled
ICYC
9.1 ns
4.55 ns
1.6
µs
8.34 ns
4.17 ns
1.6
µs
Notes:
1.
The rise and fall time of this external clock should be 2 ns maximum.
2.
Refer to Table 2-6 for a description of PDF and PDFR.
3.
Measured at 50 percent of the input transition.
4.
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock
high or low time required for correction operation, however, remains the same at lower operating frequencies;
therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as
long as the minimum high time and low time requirements are met.
Figure 2-2. External Input Clock Timing
EXTAL
VILX
VIHX
Midpoint
Note:
The midpoint is 0.5 (VIHX + VILX).
ETH
ETL
ETC
3
4
2
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com