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DSP56321RM/D 数据表(PDF) 84 Page - NXP Semiconductors

部件名 DSP56321RM/D
功能描述  24-Bit Digital Signal Processor
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

DSP56321RM/D 数据表(HTML) 84 Page - NXP Semiconductors

Back Button DSP56321RM/D Datasheet HTML 80Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 81Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 82Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 83Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 84Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 85Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 86Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 87Page - NXP Semiconductors DSP56321RM/D Datasheet HTML 88Page - NXP Semiconductors  
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Index
Index-2
interrupt and mode control 1-1
, 1-7
interrupt control 1-7
interrupt timing 2-7
external level-sensitive fast 2-10
external negative edge-triggered 2-10
interrupts
EFCOP A-12
J
Joint Test Action Group (JTAG)
interface 1-17
JTAG iii
JTAG Port
reset timing diagram 2-31
timing 2-31
JTAG/OnCE Interface signals
Debug Event signal (DE signal) 1-17
JTAG/OnCE port 1-1
, 1-2
K
keeper circuit
design considerations 4-3
M
MAP-BGA
ball grid drawing (bottom) 3-3
ball grid drawing (top) 3-2
mechanical drawing 3-10
maximum ratings 2-1
, 2-2
memory expansion port iii
mode control 1-7
Mode select timing 2-7
multiplexed bus 1-2
multiplexed bus timings
read 2-20
write 2-21
N
non-multiplexed bus 1-2
non-multiplexed bus timings
read 2-18
write 2-19
O
off-chip memory iii
OnCE module iii
Debug request 2-32
On-Chip Emulation (OnCE) module
interface 1-17
On-Chip Emulation module iii
on-chip memory iii
operating mode select timing 2-11
ordering information Back Cover
P
package
MAP-BGA description 3-2
, 3-3, 3-10
Phase-Lock Loop (PLL) 1-1
design considerations 4-4
performance issues 4-4
PLL 1-3
Port A 1-1
, 1-4, 2-12
Port B 1-1
, 1-2, 1-10
Port C 1-1
, 1-2, 1-12
Port D 1-1
, 1-2, 1-13
Port E 1-1
power 1-1
, 1-2, 1-3
power consumption
design considerations 4-3
power consumption benchmark test A-1
power management iv
program memory expansion iv
program RAM iii
R
recovery from Stop state using IRQA 2-11
reset
clock signals 1-3
interrupt signals 1-7
JTAG signals 1-17
mode control 1-7
OnCE signals 1-17
Reset timing 2-7
, 2-9
ROM, bootstrap iii
S
Serial Communication Interface (SCI) iii
, 1-1,
1-2
, 1-15
Asynchronous mode timing 2-23
Synchronous mode timing 2-23
signal groupings 1-1
signals 1-1
functional grouping 1-2
Single Data Strobe 1-2
SRAM
read access 2-13
support iv
write access 2-14
Stop mode iv
Stop state
recovery from 2-11
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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